EP80579 Datasheet, PDF (999/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-31. Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register (Sheet 3 of 3)
Description: Lockable: Suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 70h
Offset End: 73h
Size: 32 bit
Default: 00000000h
Power Well: Suspend
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
SMI_CFEN
SMI on CF Enable:
0 = Disable.
1 = Enable. When this bit is 1 and SMI on CF is 1, then
the host controller will issue an SMI.
SMI_HCHEN
SMI on HCHalted Enable:
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCHalted is
1, then the host controller will issue an SMI.
SMI_HCREN
SMI on HCReset Enable:
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCReset is 1,
then host controller will issue an SMI.
Bit Reset
Value
0b
0b
0b
Bit Access
RW
RW
RW
26.2.1.30 Offset 80h: AC - Access Control Register
Table 26-32. Offset 80h: AC - Access Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 80h
Offset End: 80h
Size: 8 bit
Default: 00h
Power Well:
Bit Range
07 :01
00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
WRT_RDONLY
Write Read only:
0 = Disables a select group of normally read-only
registers in the EHC function to be written by
software.
1 = Enables a select group of normally read-only
registers in the EHC function to be written by
software. Registers that may only be written when
this mode is entered are noted in the summary tables
and detailed description as “Read/Write-Special”. The
registers fall into two categories:
a. System-configured parameters
b. Status bits
Bit Reset
Value
00h
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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