EP80579 Datasheet, PDF (1148/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
31.2.1.3 Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports Register
Table 31-5. Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports Register
Description:
These I/O ports can
Section 31.2.1.1).
also
function
as
TSB
(see
Section
31.2.1.2)
based
on
the
settings
of
TCW
(see
View: IA F
Base Address: 0000h (IO)
Offset Start: 40h at 01h
Offset End: 40h at 01h
Size: 8 bit
Default: XXh
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
CNTP
Counter Port: Each counter port address is used to
program the
16-bit Count Register. The order of programming, either
LSB only, MSB only, or LSB then MSB, is defined with the
Interval Counter Control Register at port 43h. The counter
port is also used to read the current count from the Count
Register, and return the status of the counter
programming following a Read Back command.
Bit Reset
Value
XXh
Bit Access
RW
31.3
31.3.1
31.3.2
31.3.3
Counters
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is
typically programmed for Mode 3 operation. The counter produces a square wave with
a period equal to the product of the counter period (838 ns) and the initial count value.
The counter loads the initial count value one counter period after software writes the
count value to the counter I/O address. The counter initially asserts IRQ0 and
decrements the count value by two each counter period. The counter negates IRQ0
when the count value reaches 0. It then reloads the initial count value and again
decrements the initial count value by two each counter period. The counter then
asserts IRQ0 when the count value reaches 0, reloads the initial count value and
repeats the cycle, alternately asserting and negating IRQ0.
Counter 1, Refresh Request Signal
This counter provides the refresh request signal and is typically programmed for Mode
2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial
count value is loaded one counter period after being written to the counter I/O address.
The REF_TOGGLE bit has square wave behavior (alternate between 0 and 1) and
toggles at a rate based on the value in the counter. Programming the counter to
anything other than Mode 2 results in undefined behavior for the REF_TOGGLE bit.
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a write to port 061h.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1148
August 2009
Order Number: 320066-003US