EP80579 Datasheet, PDF (248/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-65. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 1 of
2)
Offset Start Offset End
Register ID - Description
Default
Value
00000000h 00000003h “Offset 0000h: TS_Control Register” on page 1639
00000000h
00000004h 00000007h “Offset 0004h: TS_Event Register” on page 1641
0022h
00000008h 0000000Bh “Offset 0008h: TS_Addend Register” on page 1643
0000h
0000000Ch 0000000Fh “Offset 000Ch: TS_Accum Register” on page 1643
0000h
00000010h 00000013h “Offset 0010h: TS_Test Register” on page 1644
0000h
00000014h 00000017h “Offset 0014h: TS_PPS_Compare Register” on page 1646
FFFFFFFFh
00000018h 0000001Bh “Offset 0018h: TS_RSysTimeLo Register” on page 1647
0000h
0000001Ch 0000001Fh “Offset 001Ch: TS_RSysTimeHI Register” on page 1648
0000h
00000020h 00000023h “Offset 0020h: TS_SysTimeLo Register” on page 1649
0000h
00000024h 00000027h “Offset 0024h: TS_SysTimeHi Register” on page 1650
0000h
00000028h 0000002Bh “Offset 0028h: TS_TrgtLo Register” on page 1650
0000h
0000002Ch 0000002Fh “Offset 002Ch: TS_TrgtHi Register” on page 1651
0000h
00000030h 00000033h “Offset 0030h: TS_ASMSLo Register” on page 1652
0000h
00000034h 00000037h “Offset 0034h: TS_ASMSHi Register” on page 1653
0000h
00000038h 0000003Bh “Offset 0038h: TS_AMMSLo Register” on page 1654
0000h
0000003Ch 0000003Fh “Offset 003Ch: TS_AMMSHi Register” on page 1655
0000h
0040h at 20h
0043h at 20h
“Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
Register (Per Ethernet Channel)” on page 1656
0000h
0044h at 20h
0047h at 20h
“Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event Register
Per Ethernet Channel)” on page 1658
0000h
0048h at 20h
004Bh at 20h
“Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register (Per Ethernet
Channel)” on page 1659
0000h
004Ch at 20h
004Fh at 20h
“Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register (Per Ethernet
Channel)” on page 1660
0000h
0050h at 20h
0053h at 20h
“Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per Ethernet
Channel)” on page 1661
0000h
0054h at 20h
0057h at 20h
“Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register (Per Ethernet
Channel)” on page 1662
0000h
0058h at 20h
005Bh at 20h
“Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per Ethernet
Channel)” on page 1663
0000h
005Ch at 20h
005Fh at 20h
“Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register (Per
Ethernet Channel)” on page 1664
0000h
0140h at 10h
0143h at 10h
“Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
Register (Per CAN Channel)” on page 1665
0000h
0144h at 10h
0147h at 10h
“Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register (Per CAN
Channel)” on page 1666
0000h
0148h at 10h
014Bh at 10h
“Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per CAN
Channel)” on page 1667
0000h
000001F0h 000001F3h “Offset 01F0h: TS_Aux_TrgtLo Register” on page 1668
0000h
000001F4h 000001F7h “Offset 01F4h: TS_Aux_TrgtHi Register” on page 1668
0000h
00000200h 00000203h “Offset 0200h: L2 EtherType Register” on page 1669
000088F7h
Intel^® EP80579 Integrated Processor Product Line Datasheet
248
August 2009
Order Number: 320066-003US