EP80579 Datasheet, PDF (345/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
13.0
13.1
13.2
Platform Configuration
RASUM Features - SMBus Access
Configuration registers are accessible from either the IA-32 core or from the SMBus.
The IA-32 core will be able to access all configuration registers through host
configuration cycles. Access via SMBus is read/write to the IMCH configuration
registers. The SMBus cannot use the IMCH's SM-port target interface to access any
register in the IICH or outside of CMI. Each device must have its own SMBus target
port.
CMI does not shadow the RASUM registers for the SMBus. To clear these registers, a
write access will need to be performed. The IMCH SMBus has full read/write access to
the IMCH PCI legacy registers.
The IMCH global RASUM register set and those registers applicable to logical bus#0 and
memory are implemented in Function 1 of Device 0. RASUM registers specific to other
internal devices appear in the register map for the associated device. The IMCH error
control registers are in Function 1, and are read/write accessible by the processor and
through the SMBus. The IMCH error logging registers are also available to the
processor and SMB master in Function 1. The IMCH RASUM control register and the
“CMD” registers (SERRCMD, SMICMD, etc.) which control generation of SERR#, SMI#,
and SCI# are read/write accessible by the processor and through the SMBus.
FSB-initiated accesses to configuration space registers are serviced through
configuration ring. It is perfectly legal for an SMBus access to be requested while an
FSB-initiated access is already in progress. In other words, SMBus configuration
accesses and processor configuration cycles may occur at the same time. The IMCH
supports “wait your turn” arbitration to resolve all collisions and overlaps, such that the
access that reaches the configuration ring arbiter first is serviced first while the
conflicting access is held off. An absolute tie at the arbiter is resolved in favor of the
FSB.
Platform Configuration Structure Conceptual Overview
The IMCH and IICH are physically connected by an internal interface called NSI (North
South Interface). From a configuration standpoint, NSI is logically PCI bus #0. As a
result, all devices internal to the IMCH and IICH, except host switch devices appear to
be on PCI bus #0. The system's primary PCI expansion bus is physically attached to the
IICH and, from a configuration perspective, appears to be a hierarchical PCI bus behind
a PCI-to-PCI bridge and therefore has a programmable Bus number. The PCI Express
ports appear to system software to be real PCI buses behind PCI-to-PCI bridges that
reside as devices on PCI bus #0.
CMI decodes multiple PCI Device numbers. The configuration registers for the devices
are mapped as devices residing on PCI bus #0 except for host switch devices. Each
Device Number may contain multiple functions. See Table 13-1, “PCI Devices and
Functions on Bus 0” for device and function assignments.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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