EP80579 Datasheet, PDF (191/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3
7.3.1
IMCH and IICH Registers
This section summarizes the registers found in the IMCH and the IICH.
IMCH Registers: Bus 0, Device 0, Function 0
The IMCH includes the registers listed in Table 7-9 through Table 7-11. These registers
materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 16.1,
“IMCH Registers: Bus 0, Device 0, Function 0”, and Section 16.7, “Memory Mapped I/O
for NSI Registers” for detailed discussion of these registers.
Table 7-9. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers
(Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
0Ah
0Bh
0Eh
14h
2Ch
2Eh
4Ch
50h
51h
53h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
9Ch
9Dh
9Eh
9Fh
01h
03h
05h
07h
08h
0Ah
0Bh
0Eh
17h
2Dh
2Fh
4Fh
50h
51h
53h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
9Ch
9Dh
9Eh
9Fh
“Offset 00h: VID – Vendor Identification Register” on page 391
8086h
“Offset 02h: DID – Device Identification Register” on page 391
5020h
“Offset 04h: PCICMD: PCI Command Register” on page 392
0006h
“Offset 06h: PCISTS: PCI Status Register” on page 393
0010h
“Offset 8h: RID - Revision Identification Register” on page 394
Variable
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 394
00h
“Offset 0Bh: BCC – Base Class Code Register” on page 394
06h
“Offset 0Eh: HDR - Header Type Register” on page 395
80h
“Offset 14h: SMRBASE - System Memory RCOMP Base Address Register” on
page 396
00000000h
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 396
0000h
“Offset 2Eh: SID - Subsystem Identification Register” on page 397
0000h
“Offset 4Ch: NSIBAR - Root Complex Block Address Register” on page 397
00000000h
“Offset 50h: CFG0- IMCH Configuration 0 Register” on page 398
0Ch
“Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register” on page 399
00000h
“Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register” on page 399
00h
“Offset 58h: FDHC - Fixed DRAM Hole Control Register” on page 400
00h
“Offset 59h: PAM0 - Programmable Attribute Map 0 Register” on page 401
00h
“Offset 5Ah: PAM1: Programmable Attribute Map 1 Register” on page 402
00h
“Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register” on page 403
00h
“Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register” on page 404
00h
“Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register” on page 405
00h
“Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register” on page 406
00h
“Offset 5FH: PAM6 - Programmable Attribute Map 6 Register” on page 407
00h
“Offset 9Ch: DEVPRES - Device Present Register” on page 408
33h
“Offset 9Dh: EXSMRC - Extended System Management RAM Control Register” on
page 409
00h
“Offset 9Eh: SMRAM - System Management RAM Control Register” on page 411 02h
“Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register”
on page 413
07h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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