EP80579 Datasheet, PDF (529/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-143.Offset 04h: PCICMD - PCI Command Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 04h
Offset End: 05h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
PERRE
VPS
MWIE
SCE
BME
MAE
IOAE
Parity Error Enable: This bit determines the device
behavior on detection of a parity error. See the PCI
Express* Interface Specification, Rev 1.0a, for details.
0 = Parity Errors are logged in the status register, but no
other action is taken.
1 = Normal action is taken upon detection of Parity Error,
as well as logging.
VGA palette snoop: Not applicable.
Memory Write and Invalidate Enable: Not applicable.
Special Cycle Enable: Not applicable.
Bus Master Enable: This bit controls the PCI Express*
port’s ability to issue memory and I/O read/write requests
on behalf of subordinate devices. MSI interrupt messages
are in-band memory writes, and clearing this bit disables
MSI interrupt messages.
0 = Disable. The port does not respond to any I/O or
memory transaction originating on the secondary
interface.
1 = Enable.
Memory Access Enable: Controls access to the Memory
and Prefetchable memory address ranges.
0 = Disable all of device memory space
1 = Enable
IO Access Enable: Controls access to the I/O address
range defined in the IOBASE and IOLIMIT registers.
0 = Disable device I/O space
1 = Enable
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RO
RO
RO
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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