EP80579 Datasheet, PDF (1509/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.8
LATECOL – Late Collisions Count Register
Late collisions are collisions that occur after one slot time. This register will only
increment if transmits are enabled and the device is in half-duplex mode.
Table 37-86. LATECOL: Late Collisions Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4020h
Offset End: 4023h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4020h
Offset End: 4023h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4020h
Offset End: 4023h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
LATECOL Number of packets with late collisions
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.9
COLC – Collision Count Register
This register counts the total number of collisions seen by the transmitter. This register
will only increment if transmits are enabled and the device is in half-duplex mode. This
register applies to clear as well as secure traffic.
Table 37-87. COLC: Collision Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4028h
Offset End: 402Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4028h
Offset End: 402Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4028h
Offset End: 402Bh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
COLC
Total number of collisions experienced by the transmitter
Bit Reset
Value
0h
Bit Access
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1509