EP80579 Datasheet, PDF (1556/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.7.4.4 Reset without Transition to D3
Figure 37-55.Reset without Transition to D3
CLK
RESET
Reading EEPROM
2
4
tpree
tee
tprmem ⁸ _{Memory Access Enable 9}
Read EEPROM
Wakeup Enabled
Any mode
DState
D0a
tprwdis
Dr
APM Wakeup
D0u
D0a
Note
2
4
8
9
Upon assertion of RESET the MAC will go to “Dr” state.
The deassertion edge of RESET will case the EEPROM to be re-read, and Wake Up disabled.
The system can delay an arbitrary time before enabling memory access.
Writing a 1 to the Memory Access Enable bit in the PCI Command Register will transition the MAC
from D0u to D0 state.
37.7.4.5
Timing Requirements
The MAC requires the following start-up or power state transition related timing
Table 37-148.MAC Timing
Parameter
Description
tppg
trpg
tpgrst
Power to PWR_OK
RESET stable to PWR_OK
PWR_OK assertion to RESET
deassertion.
tprmem
RESET deassertion to Memory
Access Enable
tclkpr1
CLK stopped to RESET
deassertion.
Min
0
0
0
10ms
0ns
Max.
-
-
Notes
-
The Power Management
-
specification permits access in
10ms after exiting D3 cold. PCI
2.2 gives 225 cycles.
The reset must be asserted before
the rising edge of the last cycle
before the clock is stopped.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1556
August 2009
Order Number: 320066-003US