EP80579 Datasheet, PDF (1318/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.11.1.29 Offset F4h: MADR – Message Signalled Interrupt Address Register
Table 35-147.Offset F4h: MADR: Message Signalled Interrupt Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: F4h
Offset End: F7h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
ADDR
Message Address: Written by the system to indicate the
lower 32-bits of the address to use for the MSI memory
write transaction. The lower two bits will always be written
as 0.
Bit Reset
Value
0h
Bit Access
RW
35.11.1.30 Offset F8h: MDATA – Message Signalled Interrupt Data Register
Table 35-148.Offset F8h: MDATA: Message Signalled Interrupt Data Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:7:0
Offset Start: F8h
Offset End: F9h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
DATA
Message Data: Written by the system to indicate the
lower 16 bits of the data written in the MSI memory write
DWORD transaction. The upper 16 bits of the transaction
are written as 0.
Bit Reset
Value
0h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1318
August 2009
Order Number: 320066-003US