EP80579 Datasheet, PDF (1756/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
48.4.3.9 Power Management Interface
Table 48-19. Power Management Interface Signals (Sheet 1 of 2)
Signal Name
PLTRST#
PROCHOT#
THRMTRIP#
SLP_S3#
SLP_S4#
SLP_S5#
IO Type
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
LVTTL,3.3V
Direction
Ball
Count
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
O
1
BSC
Platform Reset: The EP80579 asserts PLTRST#
to reset devices that reside on the PCI bus. The
IICH asserts PLTRST# during power-up and
when a hard reset sequence is initiated through
the 0CF9h register. PLTRST# is driven inactive a
minimum of 1 ms after both PWROK and
VRMPWRGD are driven high. PLTRST# is driven
for a minimum of 1 ms when initiated through
the 0CF9h register.
O
1
OD I/O
1
O
1
O
1
O
1
BSC
10K
(maximum) BSC
Up
BSC
BSC
BSC
Note: PLTRST# is in the 3.3V VCCPSUS well.
Processor Hot Thermal Alarm: This signal will go
active when the processor temperature
monitoring sensor detects that the processor
has reached its maximum safe operating
temperature. This indicates that the processor
Thermal Control Circuit has been activated, if
enabled.
Thermal Trip: The processor protects itself from
catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the
normal operating temperature to ensure that
there are no false trips. When low, indicates that
a thermal trip on behalf of the processor has
occurred, and corrective action will be taken
(immediately transitions the EP80579 to a S5
state). This is an open-drain signal which
optionally allows the platform to force an S5
transition.
S3 Sleep Control: SLP_S3# is for power plane
control. This signal shuts off power to all non-
critical systems when in S3 (Suspend To RAM),
S4 (Suspend to Disk), or S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane
control. This signal shuts power to
all non-critical systems when in the S4 (Suspend
to Disk) or S5 (Soft Off) state.
Note: This pin must be used to control the DRAM
power to use the EP80579 's DRAM power-
cycling feature.
S5 Sleep Control: SLP_S5# is for power plane
control. This signal is used to shut power off to
all non-critical systems when in the S5 (Soft Off)
states.
PWROK
LVTTL,3.3V I
1
Power OK: When asserted, PWROK is an
indication that core power has been stable for at
least 99ms and PCICLK has been toggling
cleanly for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is low, PLTRST#
is asserted.
Note that it is required that the core power has
been valid for 99ms prior to PWROK assertion in
order to comply with the 100ms PCI 2.3
Specification on PLTRST# deassertion.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1756
August 2009
Order Number: 320066-003US