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Intel^® EP80579 Integrated Processor
28.2
IA-32 Core Interface Signals
This section provides additional behavioral descriptions of the signals that interface
between the IICH and the IA-32 core.
28.2.1
A20M# (Mask A20)
The A20M# signal is active (low) when both of the following conditions are true:
1. The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a ‘0’.
and
2. The A20GATE input signal is a ‘0’.
The A20GATE input signal is expected to be generated by the external microcontroller
(KBC).
28.2.2 INIT# (Initialization)
The INIT# signal is active (driven low) based on any one of several events described in
Table 28-8. When any of these events occur, INIT# is driven low for 16 PCI clocks, then
driven high.
The IICH supports the coprocessor error function with the FERR#/IGNNE# pins. The
Table 28-8. INIT# Going Active
Cause of INIT# Going Active
Comment
Shutdown special cycle from IA-32 core observed on the
IICH interconnect (from IMCH).
PORT92 write, where INIT_NOW (bit 0) transitions from
a 0 to a 1.
PORTCF9 write, where SYS_RST (bit 1) was a 0 and
RST_CPU (bit 2) transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected to be
driven by the external microcontroller (KBC).
0 to 1 transition on RCIN# must occur before the IICH arms INIT#
to be generated again.RCIN# signal is expected to be high during
S3-hot and low (due to core power being off) during S3-cold, S4,
and S5 states. Transitions on the RCIN# signal in those states (or in
the transition to those states) may not necessarily cause the INIT#
signal to be generated to the .
The processor uses two processor pins, INIT# and RESET, to initiate
BIST. The processor executes BIST when INIT# is active on RESET's
falling edge. Another way to initiate BIST is to enter the RUNBIST
command through the TAP serial port.
CPU BIST
By default, CPU BIST is disabled. In order to enter CPU BIST,
software must set the RCBA.CBE bit 2 = ‘1’ and then do a full
processor reset using the CF9 register bit 2.
NOTE: A3# functions in the same manner that INIT# does as a strap
to run BIST.
function is enabled via the COPROC_ERR_EN bit (Device 31, Function 0, Offset D0, Bit
13); refer to Table 28-6 for details. FERR# is tied directly to the Coprocessor Error
signal of the . If FERR# is driven active by the , IRQ13 goes active (internally). When it
detects a write to the COPROC_ERR register, the IICH negates the internal IRQ13 and
drives IGNNE# active. IGNNE# remains active until FERR# is driven inactive. IGNNE#
is never driven active unless FERR# is active.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1102
August 2009
Order Number: 320066-003US