EP80579 Datasheet, PDF (1146/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
31.2.1
31.2.1.1
Timer Registers
Offset 43h: TCW - Timer Control Word Register
This register is programmed prior to any counter being accessed to specify counter
modes. Following reset, the control words for each register are undefined and each
counter output is 0. Each timer must be programmed to bring it into a known state.
Table 31-3. Offset 43h: TCW - Timer Control Word Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 43h
Offset End: 43h
Size: 8 bit
Default: XXh
Power Well: Core
Bit Range
07 :06
05 :04
03 :01
00
Bit Acronym
Bit Description
Sticky
CNTSEL
RWMD
CNTMD
BCDCNT
Counter Select: The Counter Selection bits select the
counter the control word acts upon as shown below. The
Read Back command is selected when bits[07:06] are
both one.
00 Counter 0 select
01 Counter 1 select
10 Counter 2 select
11 Read Back command
Read/Write Mode Selection: These bits are the read/
write control bits. The actual counter programming is done
through the counter port (40h for counter 0, 41h for
counter 1, and 42h for counter 2)
00 Counter Latch Command
01 Read/Write Least Significant Byte (LSB)
10 Read/Write Most Significant Byte (MSB)
11 Read/Write LSB then MSB
Counter Mode Selection: These bits select one of six
possible modes of operation for the selected counter.
000 0
001 1
x10 2
x11 3
100 4
101 5
Out signal on end of count (=0)
Hardware retriggerable one-shot
Rate generator (divide by n counter)
Square wave output
Software triggered strobe
Hardware triggered strobe
Binary/BCD Countdown Select:
0 = Binary countdown is used. The largest possible binary
count is 2¹⁶.
1 = Binary coded decimal (BCD) count is used. The
largest possible BCD count is 10⁴.
Bit Reset
Value
XXb
XXb
XXXb
Xb
Bit Access
WO
RWS
WO
WO
31.2.1.2
There are two special commands that can be issued to the counters through this
register, the Read Back command (Section 31.5.3) and the Counter Latch command
(Section 31.5.2). When these commands are chosen, several bits within this register
are redefined. These register formats are described in Section 31.5.
Offset 40h: TSB[0-2] - Interval Timer Status Byte Format Register
Each counter's status byte can be read following a Read Back command. If latch status
is chosen (bit 4=0, Read Back command) as a read back option for a given counter, the
next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for
counter 1, and 42h for counter 2) returns the status byte. The status byte returns the
values shown in Table 31-4.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1146
August 2009
Order Number: 320066-003US