EP80579 Datasheet, PDF (1270/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.8.1.10 Offset 2Eh: SID – Subsystem ID Register
This register is a write-once register. Once any byte in the register has been written,
the register locks against further writes until reset.
Table 35-53. Offset 2Eh: SID: Subsystem ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
SID
Subsystem ID: This field must be programmed during
BIOS initialization.
Sticky
Bit Reset
Value
Bit Access
0h
RWO
35.8.1.11 Offset 34h: CP – Capabilities Pointer Register
The CP provides the offset to the location in configuration space where the first set of
capabilities registers is located.
Table 35-54. Offset 34h: CP: Capabilities Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: DCh
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
Pointer to First Capability Structure: Value is DCh
CP
which is the config space offset of the first capability
structure.
Sticky
Bit Reset
Value
Bit Access
DCh
RO
35.8.1.12 Offset DCh: PCID – Power Management Capability ID Register
For an overview of the power management capability of AIOC devices, see Section
35.5, “Power Management of AIOC Devices”.
Table 35-55. Offset DCh: PCID: Power Management Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: DCh
Offset End: DCh
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
PCID
Capability ID: PCI SIG assigned capability record ID
(01h, power management capability)
Sticky
Bit Reset
Value
Bit Access
01h
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1270
August 2009
Order Number: 320066-003US