EP80579 Datasheet, PDF (791/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
21.4.2.2 Offset 3022h: SPIC – SPI Control
Table 21-6. Offset 3022h: SPIC - SPI Control
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3022h
Offset End: 3023h
Size: 16 bit
Default: 2005h
Power Well: Core
Bit Range
15
14
13 :08
7
6 :4
3
2
1
Bit Acronym
Bit Description
Sticky
SSMIE
DC
DBC
Rsvd
COP
SPOP
ACS
SCGO
SPI SMI# Enable: When set to 1, the SPI asserts an
SMI# request whenever the Cycle Done Status bit is 1.
Data Cycle: When set to 1, there is data that corresponds
to this transaction. When 0, no data is delivered for this
cycle, and the DBC and data fields themselves are don’t
cares.
Data Byte Count (DBC): This field specifies the number
of bytes to shift in or out during the data portion of the SPI
cycle. The valid settings (in decimal) are any value from 0
to 63. The number of bytes transferred is the value of this
field plus 1.
Note that when this field is 00_0000b, then there is 1 byte
to transfer and that 11_1111b means there are 64 bytes to
transfer.
Reserved
Cycle Opcode Pointer: This field selects one of the
programmed opcodes in the Offset 3078h: OPMENU –
Opcode Menu Configuration to be used as the SPI
Command/Opcode. In the case of an Atomic Cycle
Sequence, this determines the second command.
Sequence Prefix Opcode Pointer: This field selects one
of the two programmed prefix opcodes for use when
performing an Atomic Cycle Sequence. A value of 0 points
to the opcode in the least significant byte of the Offset
3074h: PREOP – Prefix Opcode Configuration register. By
making this programmable, the EP80579 supports flash
devices that have different opcodes for enabling writes to
the data space vs. status register.
Atomic Cycle Sequence (ACS): When set to 1 along with
the SCGO assertion, the EP80579 will execute a sequence
of commands on the SPI interface. The sequence is
composed of:
Atomic Sequence Prefix Command (8-bit opcode only)
Primary Command specified by software (can include
address and data)
Polling the Flash Status Register (opcode 05h) until bit 0
becomes 0b.
The SPI Cycle in Progress bit remains set and the Cycle
Done Status bit in Offset 3020h: SPIS – SPI Status register
remains unset until the Busy bit in the Flash Status
Register returns 0.
SPI Cycle Go (SCGO): This bit always returns 0 on reads.
However, a write to this register with a ‘1’ in this bit starts
the SPI cycle defined by the other bits of this register. The
SPI Cycle in Progress (SCIP) bit in Offset 3020h: SPIS –
SPI Status register gets set by this action. Hardware must
ignore writes to this bit while the SPI Cycle In Progress bit
is set.
Hardware allows other bits in this register to be
programmed for the same transaction when writing this bit
to 1. This saves an additional memory write.
Bit Reset
Value
00
1
0
0
0
0
1
0
Bit Access
RW
RW
RW
RV
RW
RW
RW
RWS
0
Rsvd
Reserved
1
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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