EP80579 Datasheet, PDF (432/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-46. Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 2 of 4)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 64h
Offset End: 67h
Size: 32 bit
Default: 12110000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
8 bank device Sequential Bank Activation
Restriction: No more than 4 banks may be activated in a
rolling tFAW window. Converting to clocks is done by
dividing tFAW(ns) by tCK(ns) and rounding up to next
integer value. As an example of the rolling window, if
(tFAW/tCK) rounds up to 10 clocks, and an activate
command.
This field is not valid for 4 banks device technologies like
256Mb x8 and 512 x8.
JEDEC recommendations:
1KB Page size = 37.5ns
2KB Page size = 50ns
Bit Reset
Value
Bit Access
24 :20
tFAW
Encoding
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
Others
Number of CMDCLK
delays
No restriction
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Reserved
N
00001b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
432
August 2009
Order Number: 320066-003US