EP80579 Datasheet, PDF (1511/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.12 CEXTERR – Carrier Extension Error Count Register
This register counts the number of packets received in which a carrier extension error
was signaled by the PHY (by the encoding of 0x1F on the receive data inputs while
RX_ER is asserted to the MAC) during the carrier extended time of a packet reception.
This register will only increment when the driver has receives enabled and the device is
operating at 1000Mb/s.
This counter is non-functional as the receiver doesn’t detect Carrier-Extend errors.
Table 37-90. CEXTERR: Carrier Extension Error Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 403Ch
Offset End: 403Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 403Ch
Offset End: 403Fh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 403Ch
Offset End: 403Fh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
CEXTERR Number of packets received with a carrier extension error.
Bit Reset
Value
0h
Bit Access
RC
37.6.6.13 RLEC – Receive Length Error Count Register
This register counts Receive Length Error events. A length error occurs if an incoming
packet passes the MAC address filtering (Broadcast or Individual-Address/Multicast
match) but is undersized or oversized. Packets less than 64B are deemed as
undersized; packets over 1522B are deemed oversized if RCTL.LPE=0. If RCTL.LPE=1,
then an incoming packet is only considered oversized if it exceeds 16384B.
Table 37-91. RLEC: Receive Length Error Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 4040h
Offset End: 4043h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 4040h
Offset End: 4043h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 4040h
Offset End: 4043h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 00
RLEC
Number of packets with receive length errors.
Sticky
Bit Reset
Value
0h
Bit Access
RC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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