EP80579 Datasheet, PDF (648/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.65.1 Control of delay for DQ/DQs
There are two methods to control delay:
• Adding portions of a clock cycle
• Adding portions of a clock cycle as well as delay from the WDLL
The full control is encoded by combining the appropriate bit of
WDLL_MISC.WL_PHSEL_MODE with WL_CNTL[x].WL_CNTRL as shown in Table 16-294
Table 16-294. Delay of DQ/DQS
WDLL_MISC.WL_PHSEL_MODE, WL_CNTL[x].WL_CNTRL
00xxx
01000
01011
01100
01101
10xxx
11001
11000
11011
11100
Delay
0
WDLL_DLY
1/4 CLK + WDLL_DLY
1/2 CLK + WDLL_DLY
3/4 CLK + WDLL_DLY
0
1/4 CLK
1/2 CLK
3/4 CLK
1 CLK
16.5.1.65.2 Formula to calculate delay through DLL
delay_uncomp = 100 ps (approximate value)
delay_element = (1/4 CLK period - delay_uncomp) / (DDRIOMC2.MASTCNTL + 1/
2)
WDLL_DLY = (delay_element * WL_CNTL.WDLL_CNTL)/8
16.5.1.66 Offset 298h: WDLL_MISC - DLL Miscellaneous Control
This register controls miscellaneous functions of the DDRIO DLL.
This CSR is in the memory-mapped IO region of Bus 0, Device 0, Function 0 of the
memory controller. The SMRBASE register described in Section 16.1.1.9, “Offset 14h:
SMRBASE - System Memory RCOMP Base Address Register” on page 395, provides the
base address for these registers. The offsets listed for the following registers are
relative to this base address.
The value for BAR for all registers in this section is BAR14h.
Intel^® EP80579 Integrated Processor Product Line Datasheet
648
August 2009
Order Number: 320066-003US