EP80579 Datasheet, PDF (424/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.41 Offset 78h: DRT0 - DRAM Timing Register 0
The DRT register defines the DRAM timing parameter. For the EP80579, there are 2
DRT registers that need to be programmed based on the external capabilities of the
memory devices, number of ranks/DIMM’s, supported EP80579 memory configurations
etc.
For details about the DRT1 register see “Offset 64h: DRT1 – DRAM Timing Register 1”
on page 431.
Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 1 of 7)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 242AD280h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Back-To-Back Read-Write Turn Around: This field
determines the minimum number of CMDCLK on the DQ
bus between Read-Write commands. It applies to RD-WR
pairs to any destinations (in same or different rows). The
purpose of this bit is to control the turnaround time on the
DQ bus.
The encoding below will be translated by the hardware into
a number of CMDCLK’s that will be inserted between read
write commands.
Bit Reset
Value
Bit Access
31 :29
BTBRWTA
Encoding
000
001
010
011
100
101
110
111
Command
Clocks per
Frequency
0
1
2
3
4
5
6
7
N
001b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
424
August 2009
Order Number: 320066-003US