EP80579 Datasheet, PDF (591/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.75 Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register
The Uncorrectable Error Detect Mask register controls detection of the individual errors.
An error event that is masked in this register, is treated as though the error never
happened, and is subsequently not logged in the Uncorrectable Error Status register,
nor is it ever reported. There is one mask bit corresponding to every implemented bit in
the Uncorrectable Error Status register. This register is specific to the IMCH. These bits
are sticky through reset.
Table 16-214.Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register (Sheet
1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 14Ch
Offset End: 14Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 14Ch
Offset End: 14Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 21
20
19
18
17
16
15
14
13
12
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
Reserved Reserved
00000000000b
Unsupported Request Error Detect Mask. [STICKY]:
UREDM 0 = Detect Unsupported Request Error
Y
0b
RW
1 = Disable Unsupported Request Error detection
Reserved Note: Reserved
Y
0b
RO
MTEDM
Malformed TLP Error Detect Mask. [STICKY]:
0 = Detect Malformed TLP Error
1 = Disable Malformed TLP Error detection
Y
0b
RW
Receiver Overflow Error Detect Mask. [STICKY]:
ROEDM
OPTIONAL
0 = Detect Receiver Overflow Error
Y
0b
RW
1 = Disable Receiver Overflow Error detection
Unexpected Completion Error Detect Mask.
UCEDM
[STICKY]:
0 = Detect Unexpected Completion Error
Y
0b
RW
1 = Disable Unexpected Completion Error detection
Completer Abort Error Detect Mask. [STICKY]:
CAEDM
OPTIONAL
0 = Detect Completer Abort Error
Y
0b
RW
1 = Disable Completer Abort Error detection
Completion Timeout Error Detect Mask. [STICKY]:
CTEDM 0 = Detect Completion Timeout Error
Y
0b
RW
1 = Disable Completion Timeout Error detection
Flow Control Protocol Error Detect Mask. [STICKY]:
FCPEDM
OPTIONAL
0 = Detect Flow Control Protocol Error
Y
0b
RW
1 = Disable Flow Control Protocol Error detection
PTEDM
Poisoned TLP Error Detect Mask. [STICKY]:
0 = Detect Poisoned TLP Error
1 = Disable Poisoned TLP Error detection
Y
0b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
591