EP80579 Datasheet, PDF (367/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
14.2.1.9
legacy type interrupts if so enabled in the PCI command register and MSI is not
enabled, or message signaled interrupts if so enabled in the MSI Capabilities register
(Device 2-3, Function 0, Offset 5A-5Bh).
The Root Port Control register (Device 2-3, Function 0, Offset 80-83h) enables errors to
be reported to the system via other IMCH specific methods, again on a category basis.
The Error Do Command register, selects between the four methods of system signaling,
SERR, SCI, SMI, and MCERR.
The error model outside of PCI Express includes a local FERR/NERR pair of registers in
each unit and a global FERR/NERR pair of registers that indicates which unit had
problems. The Local FERR/NERR register pair (Device 2-3, Function 0, Offset 160-163h
& 164-167h) includes PCI Express defined errors and additional detected errors within
the PCI Express unit. This register pair has three sets of error bits for the three
categories of errors: the first set for received messages, the second set for internally
detected errors (virtual messages need not have been generated), and unit specific
errors outside of the PCI Express spec, and the third set for device errors. This error
scheme sets FERR/NERR error bits regardless whether or not they were reported via
interrupt or other signaling method.
The signaling due to unit specific errors has its logic dependent on the PCI Express Unit
Error Register (Device 2-3, Function 0, Offset 140-143h). The errors flagged in this
register must be cleared before exiting the error service routine.
The signaling due to received messages has its logic dependent on the Root Error
Message Status register (Device 2-3, Function 0, Offset 130-133h). The Root Error
Status register must be cleared before exiting the error service routine.
The signaling due to internally detected PCI Express errors has its logic dependent on
the Device Status register (Device 2-3, Function 0, Offset 6E-6Fh). The Device Status
register must be cleared before exiting the error service routine.
Software must clear the global FERR first, and then the global NERR. Software then
clears the local FERR register and the local NERR register of each unit in that order.
After clearing FERR and then clearing NERR, the local FERR must be read to make sure
that remains ‘0’ indicating no more errors have occurred during the clearing of these
registers. After all units’ FERR & NERR registers have been cleared, the global FERR is
again read to ensure that no additional errors occurred during the clearing sequence.
Since the PCI Express units have more hierarchy than other units, more registers must
be cleared other than just the local FERR and NERR registers. After clearing the local
FERR & NERR, one must also clear the Root Error Status, Unit Error Status, Device
Status, Uncorrectable Error Status, and Correctable Error Status registers. One only
needs to clear the PCI Status and Secondary Status registers if these are being utilized
in a given particular error model. No logic depends on the state of any of these status
bits. If not utilized, they can be ignored.
If a PCI Express error handler is used, with no knowledge of the FERR/NERR registers,
then clear the PCI Express specific registers: Device Status, Uncorrectable Error Status,
Correctable Error Status, and Root Error Status. The IMCH specific unit errors would
not be enabled for reporting errors. Figure 14-3 helps to illustrate the relationship of
the error registers from the PCI Express* Specification.
Configurable Error Containment at the Legacy Interface
Depending on the I/O devices in use, data errors could have catastrophic effects when
allowed to propagate. The Legacy interface has the configurability of allowing the
poisoning and propagation of data errors or to stop the data from transferring at all and
escalate the data errors to the system. This is extreme behavior, which can be enabled
or disabled, in order to prevent data corruption on a critical device, and is referred to as
“stop and scream”. Refer to the Error Injection section for more details.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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