EP80579 Datasheet, PDF (1713/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
43.2
I/O Testing
The EP80579 implements JTAG Boundary Scan to allow testing of the I/O pins.
43.2.1
JTAG Boundary Scan
The EP80579 implements IEEE 1149.1 compliant JTAG Boundary Scan (BScan) on all
its interfaces withthe exception noted below.
The three high-speed interfaces, PCIe, SATA and USB2 did not implement JTAG BScan.
These are tested with an XOR chain that covers the AFEs of all 3 interfaces (Section
46.2.3, “XOR Chains”). In addition, several compliance pins were excluded from the
BScan chain to ensure proper functionality. These are listed in Table 43-4. The
Boundary Scan Chain is defined in the EP80579 BSDL file.
43.2.1.1 Pins Excluded from Boundary Scan Chain
Several critical compliance pins were excluded from the Boundary Scan chain. These
are listed below in Table 43-4.
Table 43-4. Compliance Pins Excluded from Boundary Scan Chain
Interface
RTC
ICH Misc
Power Mgmt
SMBus
CRU
LEB
DDR
VC signal
GBE
Excluded Pin(s)
RTCX1, RTCX2, RTEST_N
INTVRMEN
PWROK, RSMRST_N
INTRUDER_N
CLKS100, CLKP100, CLKN100
EXRCMP, EXRCMN
D_RCOMPX, D_DDRCRES[2:0], D_DRVCRES, D_SLEWCRES
XXTHRMDC_OUT, XXTHRMDA_IN, XXTPCD_OUT, XXTPCL_OUT, XXHFPLL_OUT
GBE_RCOMPP, GBE_RCOMPN, SYS_PWR_OK, GBE_AUX_PWR_GOOD
§§
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1713