EP80579 Datasheet, PDF (882/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.5.6
Interrupt Architecture
Table 23-77 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the 4 possible interrupt bits in I/O space, which are: PSTS.PRDIS (offset 02h,
bit 7), PSTS.I (offset 02h, bit 2), SSTS.PRDIS (offset 0Ah, bit 7), and SSTS.I (offset
0Ah, bit 2).
Table 23-77. MSI vs. PCI IRQ Actions
Interrupt Register
All bits ‘0’
One or more bits set to ‘1’
One or more bits set to ‘1’, new bit gets set to ‘1’
One or more bits set to ‘1’, software clears some (but not all) bits
One or more bits set to ‘1’, software clears all bits
Software clears one or more bits, and one or more bits is set on
the same clock.
Wire-Mode Action
Wire inactive
Wire active
Wire active
Wire active
Wire inactive
Wire active
MSI Action
No action
Send message
Send message
Send message
No action
Send message
23.5.7
Staggered Spin-up
To support staggered spin-up with legacy software, the AHCI memory space register
HCAP.SSS must be cleared, and the configuration register PCS is used to enable/disable
the port.
23.5.8 HW/SW Operation for Detecting an SATA Device Presence
23.5.8.1
Introduction
In legacy mode, the SATA controller does not generate interrupts based on hot plug/
unplug events. However, the SATA PHY does know when a device is connected (if not in
a partial or slumber state), and it is beneficial to communicate this information to host
software as this will greatly reduce boot times and resume times.
23.5.8.2
Hardware Flow
The flow for using these bits is shown in Table 23-2. The ‘PxE’ bit refers to PCS.P0E,
and PCS.P1E bits, depending on the port being checked, and the ‘PxP’ bit refers to the
PCS.P0P, and PCS.P1P bits, depending on the port being checked.
Intel^® EP80579 Integrated Processor Product Line Datasheet
882
August 2009
Order Number: 320066-003US