EP80579 Datasheet, PDF (1679/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• T3 – Strobe Timing
• T4 – Hold Timing
• T5 – Recovery Phase
For Synchronous Intel mode, the T1,T2, T3, T4, T5 timing parameters are only used for
writes. For Synchronous Intel reads, the Expansion bus controller uses the Count value
programmed in the EXP_SYNCINTEL_COUNT register to determine how many cycles
before data is valid (based on the timing parameters for a specific device) For Micron
ZBT devices, the timing parameters must be programmed to all zero since reads and
writes are synchronous.
The Expansion-bus address is used to present the 25 bits of the address [24:0] used
for the Expansion bus access accompanied by an address latch enable output signal,
EX_ALE for multiplexed devices. The address phase normally lasts two clock cycles in
multiplexed mode. The address phase may be extended by one to three clock cycles
using the T1 - Address Timing parameter, bits 29:28 in the Timing and Control
(EXP_TIMING_CS) Register for the particular Chip Select. When the address phase T1
is extended, the ALE pulse is extended and always deasserts one cycle prior to the end
of the T1 phase. The lower address bits are placed onto the data bus (i.e for a 16 bit
data bus, EX_DATA contains EX_ADDR[15:0]) along with EX_ADDR[24:0] signals
during the first cycle of the address phase. During the second cycle of the address
phase, the data bus now will output data when attempting to complete a write or tri-
state when attempting to complete a read. The address signals will retain their state.
For Synchronous Intel and Micron ZBT devices, EX_ALE acts as the address valid signal
(ADV#) and is logic 0 during the address phase and logic 1 during the continuation of a
burst or IDLE cycle.
Due to the fact that, in HPI mode of operation, it is possible to begin an access to a
busy device (EX_RDY is false), special consideration must be taken with programming
the T1 — Address Timing parameter when using the chip select in HPI mode. The T1 –
Address Timing parameter must be set to a minimum of two additional cycles (T1 must
equal to 0x2). Programming the T1 – Address Timing parameter to this value ensures
that the asynchronous EX_RDY input is sampled and available to the controlling
hardware logic before beginning the new HPI access over the Expansion bus.
The chip-select signal is presented for one Expansion bus phase before the Strobe
Phase. The chip select will be presented for the remainder of the Expansion bus cycles
(setup, strobe, and hold phases).
The Setup/Chip Select Timing phase may also be extended by one to three clock cycles,
using bits 27:26 of the Timing and Control (EXP_TIMING_CS) Register, T2 – Setup/Chip
Select Timing parameter. In HPI mode of operation, T2 is defined as the time required
by the external DSP device to drive EX_RDY false for the current access plus the time
required by the Expansion bus controller to sample and synchronize the EX_RDY signal.
The T2 – Setup/Chip Select Timing parameter must have a minimum value of two
additional cycles (T2 >= 0x2). Programming the T2 – Setup/Chip Select Timing
parameter to be three clock cycles in length ensures that when the Strobe Phase, T3,
begins, the Strobe Phase will be able to sample the EX_RDY signal and exit the Strobe
Phase at the proper time.
The Strobe Phase of an Expansion-bus access is when the read or write strobe is
applied. The 25 Expansion Bus Interface Address bits are maintained in non-
multiplexed mode or the Expansion Bus Interface Data bus is switched from address to
data when configured in multiplexed mode during the Strobe Phase.
The Strobe Phase may be extended from one to 15 clock cycles, as defined by
programming bits 25:22 of the Timing and Control (EXP_TIMING_CS) Register, T3 –
Strobe Timing parameter. In HPI mode of operation, the T3 – Strobe Timing parameter
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1679