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EP80579 Datasheet, PDF (517/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line
Intel® EP80579 Integrated Processor
16.3.1.22 Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register
This register enables various errors to generate the MCERR# signal on the FSB. When
an error flag is set in the EDMA_FERR or EDMA_NERR registers, it generates an SERR,
SMI, or SCI special cycle when enabled in the SERRCMD, SMICMD, or SCICMD
registers, or a MCERR# on the FSB when enabled in the MCERRCMD, respectively. Note
that only one message type can be enabled. All channels are expected to use the same
reporting structure, so only one 8-bit register is implemented.
Table 16-134.Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: ACh
Offset End: ACh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Descriptor Address Type/Range Error MCERR#
Enable: Generate MCERR# if bit 7, 15, 23, or 31 is set in
07
MCERR_N_DSC any of the EDMA_FERR or EDMA_NERR registers.
PERR
0 = Disable
1 = Enable
Descriptor Address Alignment Error MCERR# Enable:
Generate MCERR# if bit 6, 14, 22, or 30 is set in any of the
06
MCERR_N_DSC EDMA_FERR or EDMA_NERR registers.
PAE
0 = Disable
1 = Enable
Source Address Type/Range Error MCERR# Enable:
Generate MCERR# if bit 5, 13, 21 or 29 is set in any of the
05
MCERR_N_SRC
ERR
EDMA_FERR
0 = Disable
or
EDMA_NERR
registers.
1 = Enable
04
Reserved Reserved
Destination Address Type/Range Error MCERR#
Enable: Generate MCERR# if bit 3, 11, 19, or 27 is set in
03
MCERR_N_DST any of the EDMA_FERR or EDMA_NERR registers.
ERR
0 = Disable
1 = Enable
02
Reserved Reserved
Memory Data Parity Error MCERR# Enable: Generate
01
MCERR_N_MDP
MCERR# if bit 1, 9, 17, or 25 is set in any
EDMA_FERR or EDMA_NERR registers.
of
the
E1
0 = Disable
1 = Enable
Illegal Write Error MCERR# Enable: Generate MCERR#
if bit 0, 8, 16, or 24 is set in any of the EDMA_FERR or
00
MCERR_N_IWE EDMA_NERR registers.
0 = Disable
1 = Enable
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
517