EP80579 Datasheet, PDF (795/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 21-12. Offset 3076h: OPTYPE - Op Code Type (Sheet 2 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3076h
Offset End: 3077h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
5 :04
3 :02
1 :00
Bit Acronym
Bit Description
Sticky
OT2
OT1
OT0
Opcode Type 2: See the description for bits 1:0
Opcode Type 1: See the description for bits 1:0
Opcode Type 0: This field specifies information about the
corresponding Opcode 0. This information allows the
hardware to 1) know whether to use the address field and
2) provide BIOS protection capabilities. The hardware
implementation also uses the read vs. write information for
modifying the behavior of the SPI interface logic. The
encoding of the two bits is:
00 = No Address associated with this Opcode and Read
Cycle type
01 = No Address associated with this Opcode and Write
Cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type
Bit Reset
Value
0
0
0
Bit Access
RWS
RWS
RWS
21.4.2.9
Offset 3078h: OPMENU – Opcode Menu Configuration
This register is not writable when the SPI Configuration Lock-Down bit in Offset 3020h:
SPIS – SPI Status register is set. Eight entries are available in this register to give BIOS
a sufficient set of commands for communicating with the flash device, while also
restricting what malicious software can do. This keeps the hardware flexible enough to
operate with a wide variety of SPI devices.
It is recommended that BIOS avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. Write Enable opcodes should only be programmed in the
Offset 3074h: PREOP – Prefix Opcode Configuration.
Table 21-13. Offset 3078h: OPMENU - OPCODE Menu Configuration (Sheet 1 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3078h
Offset End: 307Fh
Size: 64 bit
Default: 00000005h
Power Well: Core
Bit Range Bit Acronym
Bit Description
63 :56
55 :48
470 :40
39 :32
31 :24
AO7
AO6
AO5
AO4
AO3
Allowable Opcode 7: See the description for bits 7:0
Allowable Opcode 6: See the description for bits 7:0
Allowable Opcode 5: See the description for bits 7:0
Allowable Opcode 4: See the description for bits 7:0
Allowable Opcode 3: See the description for bits 7:0
Sticky
Bit Reset
Value
0
0
0
0
0
Bit Access
RWS
RWS
RWS
RWS
RWS
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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