EP80579 Datasheet, PDF (381/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
15.3.1.1
15.3.1.2
15.3.1.3
S3 support requires specialized internal hardware. A request to enter the S3 power
state is communicated to the IMCH by the IICH. In response, the IMCH flushes all data
from the internal coherent write buffer, sequences all active DIMM rows into their “self-
refresh” state, and then returns an Ack_Sx special cycle to the IICH. Upon completion
of this sequence, the IMCH tolerates the removal of all clock references and power
sources, save the DDR2 interface power. DDR2 interface power must be supplied so
that the IMCH may hold the DIMMs in self-refresh. A full system initialization and
configuration sequence is required upon system exit from the S3 state, as all (non-
AUX) internal configuration information has been throughout the platform, but exit
latency is much lower than it would be from S5, as the memory image has been
maintained.
The Go_S3 message indicates that the IICH is getting ready to put the system into S3,
S4 or S5 state.
The extra internal logic support for S3 and S4 is not required for the S5 (soft off)
system power state because all data in the memory array is lost regardless, and the
coherent write buffer is architecturally part of the data stored in main memory.
Supported CPU Power States
EP80579-based platforms support the C0, C1, C2 and C3 states as defined by the
Advanced Configuration and Power Interface Specification (ACPI). This implies that the
core logic anchored by the IMCH properly understands and handles messaging between
the IMCH and the FSB to facilitate transitions into and out of these states.
Supported Device Power States
The IMCH supports all PCI-to-PMI and PCI Express messaging required to place any
subordinate device on any of its PCI Express ports into any of the defined device low
power states. Peripherals attached to the PCI segments provided via a PXH component
may be placed in any of their supported low power states via messaging directed from
the IMCH through the intervening PCI Express hierarchy. Directly attached native PCI
Express devices are not limited in their available low power states, although not all
available states support the downstream device “wake-up” semantic.
Further details about PCI Express power management support and accompanying PCI
Express and subordinate device power management support are provided in Section
15.3.3, “PCI Express Interface Power Management” on page 382.
Supported Bus Power States
No low power bus states are supported by the EP80579 on its internal NSI interface
between the IMCH and the IICH. Also, IMCH does not support placement of the IICH
only into any low-power state below D0, other than as a side-effect of placing the
entire system into one of the S3 cold, S4, or S5 states.
Significant low power mode support is provided for the several IMCH PCI Express ports,
as detailed in Section 15.3.3, “PCI Express Interface Power Management” on page 382.
15.3.2
DDR2 Interface Power Management
DDR2 self-refresh is supported as an integral piece of the S3 support.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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