EP80579 Datasheet, PDF (29/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
27.3 Power Management Register Details .................................................................1047
27.3.1 Power Management PCI Configuration Registers ........................................1047
27.3.1.1 Offset A0h: GEN_PMCON_1 - General PM Configuration 1
Register .......................................................................................1047
27.3.1.2 Offset A2h: GEN_PMCON_2 - General PM Configuration 2
Register .......................................................................................1049
27.3.1.3 Offset A4h: GEN_PMCON_3 - General PM Configuration 3
Register .......................................................................................1051
27.3.1.4 Offset B8h: GPI_ROUT - GPI Routing Control Register.........................1053
27.3.2 APM Power Management I/O-Mapped Registers .........................................1053
27.3.2.1 Offset B2h: APM_CNT - Advanced Power Management Control .Port Register
1054
27.3.2.2 Offset B3h: APM_STS - Advanced Power Management Status ..Port Register
1054
27.3.3 General Power Management I/O-Mapped Registers ....................................1055
27.3.3.1 Offset 00h: PM1_STS – Power Management 1 Status Register..............1056
27.3.3.2 Offset 02h: PM1_EN - Power Management 1 Enables Register ..............1058
27.3.3.3 Offset 04h: PM1_CNT - Power Management 1 Control Register.............1059
27.3.3.4 Offset 08h: PM1_TMR - Power Management 1 Timer Register ..............1060
27.3.3.5 Offset 10h: PROC_CNT - Processor Control Register ...........................1060
27.3.3.6 Offset 14h: LV2 - Level 2 Register....................................................1063
27.3.3.7 Offset 28h: GPE0_STS - General Purpose Event 0 Status Register ........1063
27.3.3.8 Offset 2Ch: PMBASE_GPE0_EN - General Purpose
Event 0 Enables Register ................................................................1066
27.3.3.9 Offset 30h: SMI_EN - SMI Control and Enable Register .......................1068
27.3.3.10 Offset 34h: SMI_STS - SMI Status Register .......................................1070
27.3.3.11 Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable
Register .......................................................................................1073
27.3.3.12 Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status
Register .......................................................................................1074
27.3.3.13 Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register...........................1074
27.4 SMI#/SCI Generation .....................................................................................1076
27.4.0.1 PCI Express* SCI...........................................................................1078
27.5 Dynamic Processor Clock Control......................................................................1079
27.5.1 Overview .............................................................................................1079
27.5.2 Transition Rules Among S0/Cx and Sx States............................................1080
27.5.3 S0/C0, S0/C2, Entry/Exit Timings and Sequences......................................1081
27.5.3.1
27.5.3.2
27.5.3.3
C0→C2→C0 Timings and Diagram ....................................................1081
C0→C2 Entry Sequence ..................................................................1082
C2→C0 Break Sequence .................................................................1083
27.6 Sleep States ..................................................................................................1083
27.6.1 Sleep State Overview ............................................................................1083
27.6.2 Initiating Sleep States ...........................................................................1083
27.6.3 Exiting Sleep States ..............................................................................1084
27.6.4 Sx-G3-Sx, Handling Power Failures..........................................................1085
27.7 Processor Thermal Management .......................................................................1086
27.7.1 PROCHOT# Signal for SMI# or SCI ..........................................................1086
27.7.2 Processor Passive Cooling.......................................................................1087
27.7.3 On-Demand Passive Cooling ...................................................................1087
27.7.4 Active Cooling.......................................................................................1087
27.8 Event Input Signals, Messages and Their Usage..................................................1087
27.8.1 PWRBTN# – Power Button ......................................................................1087
27.8.1.1 Power Button Override Function.......................................................1088
27.8.1.2 Sleep Button .................................................................................1088
27.8.2 RI# – Ring Indicate Signal .....................................................................1089
27.8.3 PME# – PCI Power Management Event .....................................................1089
27.8.4 SYS_RESET# Button..............................................................................1089
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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