EP80579 Datasheet, PDF (1442/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2.3
CTRL_EXT – Extended Device Control Register
This register provides extended control of device functionality beyond that provided by
the Device Control Register (CTRL).
Table 37-27. CTRL_EXT: Extended Device Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0018h
Offset End: 001Bh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0018h
Offset End: 001Bh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0018h
Offset End: 001Bh
Size: 32 bit
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 25
Bit Acronym
Bit Description
Sticky
Rsvd
Reserved
RMII gasket receive mode select:
0 = For proper 100mbps receive operation, after assertion
of the RMII CRS_DV signal on GBEn_RXCTL, the RMII
gasket requires that a minimum of two di-bits of ‘00’
appear on GBEn_RXDATA[1:0] before the preamble
appears.
1 = For proper 100mbps receive operation, the RMII
gasket requires that CRS_DV be asserted on
GBEn_RXCTL synchronously with GBE_REFCLK_RMII
and on the same cycle in which the first di-bit of the
preamble appears on GBEn_RXDATA[1:0].
Bit Reset
Value
0h
Bit Access
RV
0 is the default value of this bit and makes the RMII gasket
compatible with RMII PHYs that assert CRS_DV as soon as
24
RMII_RX_MODE the receive medium is non-idle, and subsequently drive
‘00’ on RXD[1:0] until proper receive signal decoding has
been achieved (per the RMII Specification, Revision 1.2).
Setting this bit to a 1 makes the gasket compatible with
RMII PHYs that assert CRS_DV simultaneously with the
start of the preamble driven on RXD[1:0]. While this
CRS_DV signalling mode does not scrictly conform to the
RMII specification, it is provided to allow compatibility with
PHY devices that use this alternate method of asserting
CRS_DV at the start of the packet.
0h
RW
This bit must be set to the proper state that corresponds to
the CRS_DV behavior of the attached RMII PHY, otherwise
100mbps packets cannot be properly received by the GbE.
23 : 22
21 : 16
This bit does not affect transmit operations.
LINK_MODE
Link Mode. This controls which interface is used to talk to
the link.
• 00 => GMII/MII mode
• 01 => reserved
• 10 => reserved
• 11 => reserved
• *Note that this bit is loaded from the EEPROM, if
present
Rsvd
Reserved
0h
RW
0h
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1442
August 2009
Order Number: 320066-003US