EP80579 Datasheet, PDF (1655/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.16 Offset 003Ch: TS_AMMSHi - Auxiliary Master Mode Snapshot High
Register
Register
Name
TS_AMMSHi
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMMS_High
Table 41-26. Offset 003Ch: TS_AMMSHi Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 0000003Ch
Offset End: 0000003Fh
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 0
Bit Acronym
Bit Description
Sticky
AMMS_High
When the board is operating in Master mode, it receives a
general-purpose input signal for synchronization of
snapshots and time. This general-purpose input,
ammssig, is synchronized by the system clock in the
Time Sync logic before it is used.
Note: The processor can configure the GPIO as an
output, but it will always be an input-only to the
Time Sync block.
When the AMMS snapshot occurs, the snm indication in
the Time Sync Event register is asserted. No new
snapshots in the AMMS register pair are captured until the
firmware writes a ‘1’ back to the snm bit to clear the
snapshot indication.
Bit Reset
Value
0000h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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