EP80579 Datasheet, PDF (1641/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.2 Offset 0004h: TS_Event - Time Sync Event Register
Register
Name
TS_Event
Access
(See below.) Reset Value 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Reserved)
Table 41-12. Offset 0004h: TS_Event Register (Sheet 1 of 2)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000004h
Offset End: 00000007h
Size: 32 bits
Default: 0022h
Power Well: Core
Bit Range
31 : 10
9: 9
8: 8
7: 6
5: 5
4: 4
3: 3
Bit
Acronym
Bit Description
Sticky
RSVD Reserved for future use.
GBe1_mii_mode status:
gbe1_mode “1” indicates the gbe 1 port is running in MII mode
“0” indicates the gbe 1 port is running in GMII mode
GBe0_mii_mode status:
gbe0_mode “1” indicates the gbe 1 port is running in MII mode
“0” indicates the gbe 1 port is running in GMII mode
RSVD Reserved for future use.
Auxiliary Target Time Interrupt Pending. This bit is the
Auxiliary Target Time interrupt pending indication. When this
bit is set, it indicates that the Auxiliary Target Time interrupt
condition has occurred, which means that the System Time
value has reached the 64-bit Auxiliary Target Time register
value. If atm in the Time Sync Control register is set, the
interrupt will be passed to the Host processor. To clear this
atp condition and also the interrupt to the Host if no other sources
are driving it, the firmware must write a ‘1’ to the atp bit. To
prevent an immediate reoccurrence of the auxiliary target
time interrupt, the processor should first write a new value to
the Auxiliary Target Time register and then clear the condition.
This bit is set at power-up since both the System Time and the
Auxiliary Target Time are reset at power-up to
0x0000000000000000.
PPS Match. This event bit sets when the lower 32 bits of the
system time register is equal to the 1PPS Compare register.
When this signal is asserted high, an interrupt will be
pps generated to the Host on the ts_intreq if the ppsm bit in the
Time Sync Control register is also set. This signal also drives
the ts_pps output pin of the TimeSync block. The user will
clear pps by writing a '1' to it.
snm
AMMS Snapshot. This event bit sets when the system time
register value is captured in the Auxiliary Master Mode
Snapshot register upon an active high level on a general
purpose input, ammssig.
• When this signal is asserted high, an interrupt will be
generated to the Host on the ts_intreq if the amm bit in
the Time Sync Control register is also set.
• To clear snm, write a ‘1’ to it.
Bit Reset
Value
x
0h
0h
0h
1
0h
0h
Bit Access
RO
RO
RO
RO
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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