EP80579 Datasheet, PDF (1549/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.7
Note:
37.7.1
37.7.2
Power Management
Power Management may be disabled via bits in the Initialization Control Word which is
loaded from the EEPROM during power-up reset. Even when disabled, the Power
Management register set is still present.
The following Power Management related features are supported:
• Power states of D0 & D3hot
• Support of optional D3cold for GbE0
• Power(D3) < Power(D0)
• Wake-up
Assumptions
The following assumptions apply:
• Prior to transition from D0 to the D3 state, the OS will ensure the device driver has
been disabled and all pending bus transactions are complete or terminated cleanly.
• Per the PCI power Management Specification (revision 1.1, section 5.4), software
“will need to perform a full re-initialization of the function including its PCI
Configuration Space.” On a transition from D3 to D0u state, all of the PCI
Configuration space is reset.
• The driver will set up the wake up filters prior to the system transitioning the GbE
to D3 state.
• No wakeup capability, except APM Wakeup if enabled in the EEPROM, is required
after the system puts the MAC in D3 state and then returns the MAC to D0.
• If the APMPME bit in the Wake Up Control Register (WUC.APMPME) bit is 1, it is
permissible to assert GBE_PME_WAKE even when PME_En is 0.
• No wakeup capability, except APM Wakeup if enabled in the EEPROM, is required
after the system asserts, then deasserts RESET_N.
• The deassertion (rising) edge of RESET_N will put the controller in D0u state.
• The system will never deactivate the internal bus clock without asserting RESET_N.
• Any time PWR_OK is asserted all power supplies are stable and RESET_N is stable.
D3cold support
If the D3Cold Wake Up Capability Advertisement Enable bit of the Device Control
Register (CTRL.ADVD3WUC) is set to '1', the D3Cold capability may be advertised (if 0,
the capability will not be advertised). When 1, the EP80579 will then use the
AUX_PWR_PRESENT input as an indication of whether auxiliary power is available to
the GbE controller, and if AUX_PWR_PRESENT=1 will advertise D3cold Wake Up support
in the PCI Capabilities list for that GbE controller.
If D3cold is supported, the PME_En and PME_Status bits of the Power Management
Control/Status Register (PMCSR), as well as shadow bits in the Wake Up Control
Register (WUC), are not reset by UNIT_RESET. However, if D3cold Wake Up is not
supported they will always be reset on the deassertion (falling edge) of UNIT_RESET.
Note that AUX_PWR_PRESENT is level sensitive and is sampled at assertion of
AUX_PWR_GOOD from the EEDI pin. EEDI must be pulled high to indicate that
AUX_PWR_PRESENT is a ‘1’. EEDI must be pulled low to indicate that
AUX_PWR_PRESENT is a “0’. EEDI MUST be either pulled up or down.
AUX_PWR_PRESENT may not be left indeterminate.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1549