EP80579 Datasheet, PDF (621/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.23 Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register
This register determines the DDR I/O FIFO write pointer fine delay timing for DQS8
signals when reading from rank 0 or rank 1
Table 16-247.Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register
Description: WPTRTC1: Write pointer timing control
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: D0h
Offset End: D0h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
7 :04
3 :00
Bit Acronym
Bit Description
Reserved
DQS08
Reserved
DQS8 write pointer fine delay
Sticky
Y
Bit Reset
Value
0h
0h
Bit Access
RO
RW
16.5.1.24 DDQSCVDP and DDQSCADP
This set of 4 registers defines two 64 bit long data patterns used in the DQS Delay
Calibration. They are only used when DCALCSR.BASPAT is low. The 64 bit patterns
cover a data burst that is 32 DRAM clock cycles long. The DDQSCVDP registers define
the “victim” pattern, and the DDQSCADP defines the “aggressor” pattern. The victim
pattern is applied to one bit of each byte of the DDR data bus for 32 clock cycles, and
the aggressor pattern is applied to all other bits. The victim pattern is applied in turn to
each bit of each byte, creating a complete data pattern that is 8*32 data cycles long.
16.5.1.25 Offset D4h: DDQSCVDP0 - DQS DELAY CALIBRATION VICTIM PATTERN
0 Register
This register defines the last 32 bits of the 64 bit long “victim” data pattern.
Table 16-248.Offset D4h: DDQSCVDP0 - DQS Delay Calibration Victim Pattern 0 Register
Description: DDQSCVDP0: DQS Delay Cal Pattern
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: D4h
Offset End: D7h
Size: 32 bit
Default: aaaa0a05h
Power Well: Core
Bit Range
31 :00
Bit Acronym
VP0
Victim pattern 0
Bit Description
Sticky
Bit Reset
Value
aaaa0a05h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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