EP80579 Datasheet, PDF (1276/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.9.1.3
Offset 02h: DID – Device Identification Register
This 16-bit register combined with the Vendor Identification register uniquely identifies
any PCI device. Each CAN controller has its own device ID. Writes to this register have
no effect.
Table 35-63. Offset 02h: DID: Device Identification Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: 02h
Offset End: 03h
Size: 16 bit
Default: 503Ah
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
DID
Device Identification Number: This is a 16-bit value
assigned to the CAN controller #2 device.
Sticky
Bit Reset
Value
Bit Access
503Ah
RO
35.9.1.4 Offset 04h: PCICMD – Device Command Register
Table 35-64. Offset 04h: PCICMD: Device Command Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:4:0
Offset Start: 04h
Offset End: 05h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:5:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0h
Power Well: Core
Bit Range
15 : 11
10
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
INTD
FBTB
SER
Reserved
PER
VPS
MWE
SS
BM
MEM
IO
Reserved
Interrupt Disable
Fast Back-to-Back Enable
SERR# Enable
Reserved
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate
Special Cycle
Bus Master Capable
Memory Space Enable: Setting this bit enables access to
the memory regions the device claims through its BARs.
I/O Space Enable: The device does not implement this
functionality since it claims no I/O regions. The bit is
hardwired to 0.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RW
RO
RO
RV
RO
RO
RO
RO
RO
RW
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1276
August 2009
Order Number: 320066-003US