EP80579 Datasheet, PDF (546/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.28 Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register
Hot Plug is not supported.
This register is for vendor specific commands.
Table 16-167.Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 45h
Offset End: 45h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 45h
Offset End: 45h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 04
03
02
Bit Acronym
Bit Description
Sticky
Reserved
CTOD
HGD
Reserved
Completion TO Timer Disable:
0 = The completion Timeout Timer is enable.
1 = The completion Timeout Timer is disabled.
Hot Plug is not supported BIOS must set this bit to
‘1’
Hot plug GPE Disable:
0 = Enables reporting of Hot Plug interrupts via the legacy
GPE mechanism.
1 = Disables reporting of Hot Plug interrupts via the
legacy GPE mechanism. This bit must be set when Hot
Plug interrupts are to be reported via the interrupt
(INTx or MSI) signaling mechanism.
Bit Reset
Value
0b
0b
0b
Bit Access
RW
RW
Training Control Loopback Enable:
0 = Disabled
01
TCLE
1 = Enabled - If this bit is a 1 when the TS1/TS2 ordered-
sets are transmitted, the “Enable Loopback” bit is set
in the training control symbol
PME Turn Off Request:
0 = Cleared by hardware when the acknowledge is
00
PMETOR
returned from the link. The bit is also cleared when
the link layer is in the DL_down state.
1 = Set by software if link layer is in the DL_UP state.
0b
RW
0b
RWS
Intel^® EP80579 Integrated Processor Product Line Datasheet
546
August 2009
Order Number: 320066-003US