EP80579 Datasheet, PDF (380/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.2.2
15.2.2.1
15.2.2.2
Suggested SMBus Usage Models
Remote Error Handling
The EP80579 supports error escalation via both SMI and MCERR FSB signaling, thus
error handling may be implemented in system management mode (SMM) software,
machine check architecture (MCA) software, or a combination of the two. Such
software could direct a BMC with an integrated NIC to “call home” when errors are
reported by the IMCH. The BMC could then interrogate internal IMCH error logging
registers under remote control across the network interface, providing full identification
and isolation of reported errors as described elsewhere in this document. The
possibility also exists for remotely managed reconfiguration via the SMBus target port,
as well as remotely managed system reboot via the BMC (if necessary).
Remote Platform Monitoring
The SMBus target also provides a sophisticated BMC with the capability to monitor the
health of an EP80579-based platform, such that statistics on correctable error location
and frequency may be tracked remotely in an effort to anticipate and prevent more
serious failures.
The IMCH includes significant RASUM functionality on both its memory subsystem and
its PCI Express interfaces. Some types of errors are expected at a modest frequency
within a platform of this complexity, and the IMCH provides internal hardware to track
the frequency of such errors. These include correctable ECC errors on the memory
interface, as well as transient communication errors on the high-speed serial PCI
Express interfaces – refer to Chapter 14.0, “RAS Features and Exception Handling” for
further details.
The BMC could be remotely directed to periodically poll the internal error logging
registers of the IMCH, permitting a remote management software package to maintain
a running profile of error types and frequencies experienced by an EP80579-based
platform. Changes in error frequency or type could be flagged by the remote
monitoring software to prompt follow-up preventative maintenance on the platform.
15.3
Platform Power Management Support
The IMCH is compatible with the PCI Bus Power Management Interface Specification,
Revision 1.1 (referred to here as PCI-to-PMI). The IMCH is also compatible with the
Advanced Configuration and Power Interface Specification, Rev. 2.0 (ACPI). The
EP80579 is designed to operate seamlessly with operating systems employing these
specifications.
The anticipated implementation for platform power management control is an add-on
component connected to the IICH component of the core logic via its LPC and/or SMBus
interfaces.
15.3.1
Supported System Power States
The IMCH and the system power states are analogous, thus no “device” power states
are defined for the IMCH. As a result, the IMCH power state may be directly inferred
from the system power state.
Like all systems, EP80579-based platforms must support the S0 (fully active) state at a
minimum. The IMCH also supports S1 (Idle), S3 cold (suspend to RAM), S4 (suspend to
disk), and S5 (soft off).
S2 (power-on suspend) and S3 hot are not supported.
Intel^® EP80579 Integrated Processor Product Line Datasheet
380
August 2009
Order Number: 320066-003US