EP80579 Datasheet, PDF (980/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.3 Offset 04h: CMD - Command Register
Table 26-5. Offset 04h: CMD - Command Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :11
10
09
08
07
06
05
04
03
Bit Acronym
Bit Description
Sticky
Reserved Reserved
INT_DIS
Interrupt Disable:
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the
interrupt controller. The corresponding Interrupt
Status bit is not affected by the interrupt enable.
This bit defaults to '0'.
This bit is added as part of the Conventional PCI 2.3
Specification.
FBE
Fast Back to Back Enable: Reserved as '0'.
SERR_N_EN
SERR# Enable:
0 = The EHC is disabled from generating (internally)
SERR#
1 = The EHC is capable of generating (internally) SERR#
in the following cases:
• Reception of status other than “Successful” on a
memory read completion (if SERR on Aborts Enable is
also set)
• Detection of an address or command parity error and
the Parity Error Response bit is set
• Detection of a data parity error (when the data is
going to the EHC) and the Parity Error Response bit is
set
• Since USB 2.0 logic does not support parity checking,
bit 6 is never set.
WCC
Wait Cycle Control: Reserved as '0'.
PER
Parity Error Response: Reserved as ‘0’.
VPS
VGA Palette Snoop: Reserved as '0'.
PMWE
Postable Memory Write Enable: Reserved as '0'.
SCE
Special Cycle Enable: Reserved as '0'.
Bus Master Enable:
0 = Clearing the BME bit shuts down the EHC DMA
engines in the same manner that clearing the Run/
Stop does. However, the schedule status bits and the
HCHalted bit do not change based on the BME value
1 = Acts as a master on the PCI bus for USB transfers.
Bit Reset
Value
00h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RO
RW
RO
RW
02
BME
Notes: Notes on the EHC implementation:
• Writes to change this bit occur immediately.
Specifically, a write followed by a read will return the
updated value.
• When the BME bit is changed from 1 to 0, the EHC will
cease accessing main memory within 2 microframes
(250 µs). During this time, any number of reads and/
or writes to memory may occur.
0h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
980
August 2009
Order Number: 320066-003US