EP80579 Datasheet, PDF (315/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
12.3.6
list and examine the state of the Channel Resume bit when the Suspend bit is
cleared. As in the prior case, the channel will re-read the current chain descriptor to
update NDAR/NDUAR, load the first appended chain descriptor, and resume
execution. The only difference in this case is that the re-read operation on the
current chain description was required for proper execution (in the prior case it was
wasted effort, but did not result in erroneous behavior). If the channel had
completed execution of the terminal chain descriptor and set the “end of chain”
status bit, this bit is automatically cleared when the channel resumes operation.
• If the current transfer had a non-fatal error, it follows one of the above cases. If the
error is fatal, the channel will abort, and the software must take proper action and
restart the EDMA transfer. Note that the channel will ignore the state of the
Channel Resume bit if the abort status has not been cleared from the CSR. This
simplifies the case of linked list append, as software need not take extra steps to
verify that no errors exist prior to setting the Channel Resume bit. The normal
polling or interrupt mechanism may handle the error without interacting with the
append routine.
Software is at liberty to modify the Next Descriptor Address fields of the terminal chain
descriptor at any time after setting the Suspend bit in the CCR – there is no
requirement that software verify that the channel has gone idle prior to modifying the
memory image. Also, software does not need to verify that the channel has completed
execution of the current chain descriptor and acknowledged Suspend EDMA prior to
issuing the final update to CSR that sets the Channel Resume bit. The hardware
interlock will cover the case where the end of the chain descriptor is reached during the
append sequence, but proper operation is guaranteed regardless of whether the
interlock is exercised.
A further simplification to the linked list append sequence is possible in the case of
chain descriptors located strictly below the 4 GB boundary in memory; that is, in the
case where NDUAR of the terminal descriptor is zero and only NDAR contains asserted
bits. Under these conditions, it is safe to issue the NDAR write cycle without first
suspending operation, because there is no risk of a hybrid NDAR/NDUAR pair retrieved
by the channel. If desired, software could take the simplified approach of issuing the
descriptor update followed by a CCR write to set the Channel Resume bit. In all cases,
this will result in successful execution of the appended chain irrespective of current
execution status.
Splicing a Descriptor Chain into a Linked List
Software may utilize a slight modification of the algorithm described in “Appending to a
Descriptor Chain” on page 314 to splice a new descriptor or chain of descriptors into
the chain already executing. Such an operation would be useful to provide service to a
higher priority EDMA transfer without aborting work already in progress.
The steps required to splice into a chain are as follows:
1. Write to the CCR to set the Suspend EDMA bit.
2. Read the CDAR/CDUAR pair to determine which chain descriptor the EDMA channel
is currently executing.
3. Read the Next Descriptor Address field of the current chain descriptor, and write the
retrieved address into the Next Descriptor Address field of the terminal chain
descriptor in the linked list to be spliced-in.
4. Write the address of the descriptor (or lead descriptor of the chain) to be spliced-in
into the Next Descriptor Address field of the current descriptor (in memory).
5. Write to the CCR to clear the Suspend bit and set the Channel Resume bit.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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