EP80579 Datasheet, PDF (633/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.5.1.40 Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed
Register
Note: If LFSR operation is selected, seed value of all 1s will NOT be able to generate
random numbers. Pattern will remain all 1s.
Table 16-265.Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed
Register
Description: MBLFSRSED: Memory Test Circular Shift and LFSR Seed
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 1A4h
Offset End: 1A7h
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
Sticky
MemBIST LFSR Seed
MBLFSRSED This 32 bit register will be used as the initial data seed for Y
LFSR or Circular shift data pattern.
Bit Reset
Value
0h
Bit Access
RW
16.5.1.41 Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer
Register
Table 16-266.Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer Register
Description: MBFADDRPTR: Memory Test Failure Address Pointer Register
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 1A8h
Offset End: 1ABh
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
Sticky
This 32 bit register designates which MemBIST failures to
log in the available failure address locations.
The default value of this register is zero. It means
MemBIST always logs beginning with the first failure. If it
is programmed to hex A (10 in decimal), MemBIST will log
MBFADDRPTR ^{failures starting from the11th failure.}
Y
The corresponding MB_ERR_DATA0/1/2/3 registers will
log corrupted data in the first through fourth designated
failure addresses.
Note: this register does not affect the MBDATA failure bit
location accumulators.
Bit Reset
Value
00000000h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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