EP80579 Datasheet, PDF (1602/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 39-20. Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
000000B0h
Offset Start: at 20h
Offset End: 000000B3h
at 20h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
000000B0h
Offset Start: at 20h
Offset End: 000000B3h
at 20h
Size: 32 bit
Default: XXXXXXXh
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
IDE
RTR
RSVD
Extended identifier bit
Remote bit
Reserved
Sticky
Bit Reset
Value
Xh
Xh
Xh
Bit Access
RW
RW
RW
39.6.1.16 Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR
Note:
These registers are implemented in the SRAM which does not have the capability to
mask writes to reserved bits. Therefore, reserved bits in this CSR will be RW. Software
should treat these bits as reserved and not change the reset value of these bits.
Note:
These registers are implemented in SRAM which is not initialized at power-up or upon
reset. So before enabling the CAN, software needs to update these CSR’s with the reset
values.
Table 39-21. Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
000000B4h
Offset Start: at 20h
Offset End: 000000B7h
at 20h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
000000B4h
Offset Start: at 20h
Offset End: 000000B7h
at 20h
Size: 32 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range
31 :03
02
01
00
Bit Acronym
Bit Description
Identifier
IDE
RTR
RSVD
Identifier
Extended identifier bit
Remote bit
Reserved
Sticky
Bit Reset
Value
Xh
Xh
Xh
Xh
Bit Access
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1602
August 2009
Order Number: 320066-003US