EP80579 Datasheet, PDF (1615/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 40-5. Offset 08h: SSSR - SSP Status Register Details (Sheet 2 of 2)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:6:0
Offset Start: 08h
Offset End: 0Bh
Size: 32 bit
Default: 0000F004h
Power Well: Core
Bit Range
07
06
05
04
03
02
01 :00
Bit Acronym
Bit Description
ROR
RFS
TFS
BSY
RNE
TNF
Reserved
Receive FIFO Overrun:
0 = Receive FIFO has not experienced an overrun
1 = Attempted data write to full Receive FIFO, request
interrupt
Receive FIFO Service Request:
0 = Receive FIFO level is below RFT threshold, or SSP
disabled.
1 = Receive FIFO level is at or above RFL threshold,
request interrupt
Transmit FIFO Service Request:
0 - Transmit FIFO level exceeds TFT threshold, or SSP
disabled
1 - Transmit FIFO level is at or below TFL threshold,
request interrupt
SSP is busy
0 = SSP is idle or disabled
1 = SSP currently transmitting or receiving a frame
Receive FIFO not empty.
0 - Receive FIFO is empty
1 - Receive FIFO is not empty
Transmit FIFO not Full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
Reserved
Sticky
Bit Reset
Value
Bit Access
y
0b
RWC
0b
RO
0b
RO
0b
RO
0b
RO
1b
RO
0h
RV
40.4.3.2
40.4.3.3
40.4.3.4
Transmit FIFO Not Full Flag (TNF) (Read-Only, Non-Interruptible)
The transmit FIFO not full flag (TNF) is a read-only bit that is set whenever the transmit
FIFO contains one or more entries that do not contain valid data. TNF is cleared when
the FIFO is completely full. This bit can be polled when using programmed I/O to fill the
transmit FIFO over its half-way mark. This bit does not request an interrupt.
Receive FIFO Not Empty Flag (RNE) (Read-Only, Non-Interruptible)
The receive FIFO not empty flag (RNE) is a read-only bit that is set whenever the
receive FIFO contains one or more entries of valid data and is cleared when it no longer
contains any valid data. This bit can be polled when using programmed I/O to remove
remaining bytes of data from the receive FIFO since CPU interrupt requests are only
made when the Receive FIFO Threshold has been met or exceeded. This bit does not
request an interrupt.
SSP Busy Flag (BSY) (Read-Only, Non-Interruptible)
The SSP busy (BSY) flag is a read-only bit that is set when the SSP is actively
transmitting and/or receiving data and is cleared when the SSP is idle or disabled
(SSE=0). This bit does not request an interrupt.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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