EP80579 Datasheet, PDF (548/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.31 Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register
This register is for vendor specific commands.
Table 16-170.Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 48h
Offset End: 48h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 48h
Offset End: 48h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 01
00
Bit Acronym
Bit Description
Reserved
DPSSEN
Reserved
NOTE: This register bit must always be disabled or
undefined behavior will result.
0 = Disable
1 = Enable
Sticky
Bit Reset
Value
00h
0b
Bit Access
RW
16.4.1.32 Offset 50h: PMCAPID - Power Management Capabilities
Structure Register
This register identifies the capability structure and points to the next structure.
Table 16-171.Offset 50h: PMCAPID - Power Management Capabilities Structure Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 50h
Offset End: 50h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 50h
Offset End: 50h
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
CAP_ID
This field has the value 01h to identify the CAP_ID
assigned by the PCI SIG for vendor dependent capability
pointers.
Bit Reset
Value
01h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
548
August 2009
Order Number: 320066-003US