EP80579 Datasheet, PDF (197/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.3
EDMA Engine Registers: Bus 0, Device 1, Function 0
The EDMA engine includes the registers listed in Table 7-13 and Table 7-14. These
registers materialize in PCI configuration and memory (via PCI BAR) spaces. See
Section 16.3, “EDMA Registers: Bus 0, Device 1, Function 0” and Section 16.6,
“Memory Mapped I/O for EDMA Registers” for detailed discussion of these registers.
Table 7-13. Bus 0, Device 1, Function 0: Summary of EDMA PCI Configuration Registers
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
0Ah
0Bh
0Eh
10h
2Ch
2Eh
34h
3Ch
3Dh
40h
80h
84h
88h
A0h
A4h
A8h
ACh
B0h
B4h
B8h
01h
03h
05h
07h
08h
0Ah
0Bh
0Eh
13h
2Dh
2Fh
34h
3Ch
3Dh
40h
83h
87h
88h
A0h
A4h
A8h
ACh
B3h
B7h
B9h
“Offset 00h: VID - Vendor Identification Register” on page 502
8086h
“Offset 02h: DID - Device Identification Register” on page 502
5023h
“Offset 04h: PCICMD - PCI Command Register” on page 503
0000h
“Offset 06h: PCISTS - PCI Status Register” on page 504
0010h
“Offset 08h: RID - Revision Identification Register” on page 504
Variable
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 505
80h
“Offset 0Bh: BCC - Base Class Code Register” on page 505
08h
“Offset 0Eh: HDR - Header Type Register” on page 505
00h
“Offset 10h: EDMALBAR - EDMA Low Base Address Register” on page 506
00000000h
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 506
0000h
“Offset 2Eh: SID - Subsystem Identification Register” on page 507
0000h
“Offset 34h: CAPPTR - Capabilities Pointer Register” on page 507
B0h
“Offset 3Ch: INTRLINE - Interrupt Line Register” on page 507
00h
“Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 508
01h
“Offset 40h: EDMACTL - EDMA Control Register” on page 508
08h
“Offset 80h: EDMA_FERR - EDMA First Error Register” on page 509
00000000h
“Offset 84h: EDMA_NERR - EDMA Next Error Register” on page 511
00000000h
“Offset 88h: EDMA_EMASK - EDMA Error Mask Register” on page 513
00h
“Offset A0h: EDMA_SCICMD - EDMA SCI Command Register” on page 514
00h
“Offset A4h: EDMA_SMICMD - EDMA SMI Command Register” on page 515
00h
“Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register” on page 516
00h
“Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register” on page 517 00h
“Offset B0h: MSICR - MSI Control Register” on page 518
00020005h
“Offset B4h: MSIAR - MSI Address Register” on page 519
FEE00000h
“Offset B8h: MSIDR - MSI Data Register” on page 520
0000h
Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 1 of 3)
Offset Start Offset End
Register ID - Description
00h
03h
“Offset 00h: CCR0 - Channel 0 Channel Control Register” on page 653
04h
07h
“Offset 04h: CSR0 - Channel 0 Channel Status Register” on page 656
Default
Value
00000000h
00000000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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