EP80579 Datasheet, PDF (520/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.3.1.25 Offset B8h: MSIDR - MSI Data Register
The MSI Data Register (MSIDR) contains all the data-related information to route MSI
interrupts.
Table 16-137.Offset B8h: MSIDR - MSI Data Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: B8h
Offset End: B9h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
14
13 : 12
11
Bit Acronym
Bit Description
Sticky
TRGMD
DLVSTS
Reserved
DSTNMD
Trigger Mode: Software must set this to be the same as
the corresponding bit in the I/O Redirection Table for that
interrupt.
0 = Edge
1 = Level
Delivery Status: If using edge-triggered interrupts, this is
always 1, since only the assertion is sent. If using level-
triggered interrupts, then this bit indicates the state of the
interrupt input.
Reserved
Destination Mode: Software must set this to be the same
as bit 2 of MSIAR.
0 = Physical
1 = Logical
Bit Reset
Value
0b
0b
00b
0b
Bit Access
RW
RW
RW
10 : 08
07 : 00
DLVMD
INTRPTV
Delivery Mode: Software must set this to be the same as
the corresponding bits in the I/O Redirection Table for that
interrupt.
000 Fixed
001 Lowest Priority
010 SMI/PMI
011 Reserved
100 NMI
101 INIT
110 Reserved
111 ExtINT
Interrupt Vector: Software must set this to be the same
as the corresponding bits in the I/O Redirection Table for
that interrupt.
0h
RW
00h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
520
August 2009
Order Number: 320066-003US