EP80579 Datasheet, PDF (175/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
6.2
BIOS Boot Flow (Initialization)
After hardware reset of the EP80579 and once IA -32 core has executed the reset
micro-code, the IA 32 core resteers to reset vector (0xFFFF_FFF0) and starts fetching
from BIOS code boot rom. BIOS starts execution from the reset vector regardless of
whether wake is from S3, S4, or S5. To determine that it is S3 resume, BIOS checks
the SUS_TYP field in the power management controller. If it is not S3, then normal boot
occurs. If it is S3, then BIOS also checks the power failure bits (PWRBTNOR_STS,
PWR_FLR, PWROK_FLR). If these are set to one, then memory contents cannot be
relied on and normal boot is followed. If it is an S3 resume and the power failure bits
are not set, then the S3 boot path is followed. The normal boot path is that used for
cold reset and for S4/S5 resume. From a BIOS perspective there is no difference
between S4 and S5. The following steps describe the boot sequence after reset before
handover to OS.
Figure 6-8. BIOS Boot Flow (Cold Boot, S3/S4->S0)
Hard Reset
1) SCePlUecPt OBCSP
2) Read/Retrieve
Memory CFG
3) Initialize
Memory
4) Shadow BIOS
5) Configure PCI-
Express Ports.
6) Enumerate PCI
8) Interrogate and
Clear Error Regs
9) APIC
Configuration
10) Enable SMM
This step is automatic and precedes any software influence on chipset configuration.
Power-On-Configuration is propagated across the FSB,. BREQ0# is asserted to select a
boot-strap CPU, and MCH strapping options are sampled.
* On cold reset, BIOS reads the SPD registers in DIMM via SMBus. BIOS finds the DDR
type, DDR frequency and configures the gearing ratio. BIOS uses the information to
programDRA, DRB, DRC and DRT registers in IMCH. BIOS enables the DDR clock.
* On S3->S0, BIOS retrieves the memory table intact from non-volatile memory, and
uses that information directly to program DRA, DRB, DRC, and DRT registers.
* On cold reset, BIOS calibrates and configures IMCH and DDR. BIOS may also run
diagnostic tests on populated memory at this point to verify no ill-effects from reset.
Initialize all populated memory to all "0"s with good ECC codes. If desired, BIOS may also
run diagnostic tests on populated memory at this point to verify no ill-effects from reset.
* On S3->S0, BIOS retrieves the prior configuration.
BIOS copies required BIOS code up from the FWH via ICH to the desired location in
main memory. Program the PAM registers to reflect the correct shadowing settings.
* For cold reset, BIOS reads the PCI-Express port configuration register and configure
ports which are successfully trained.
* For S3/S4->S0, BIOS retrieves the expected PCI-Express port configuration from
NVRAM/Disk. BIOS must then read the PCI-Express port status registers, configure the
ports which successfully trained, and update the MCH configuration map (device present
bits) to reflect MCH environment.
BIOS execute a standard PCI scan in incrementing BUS and DEVICE number order,
program primary/secondary/subordinate bus# registers, and aggregate the total memory
required for each logical PCI-Express port. At the end of this step, the PCI IO, M, PM,
TOLM, and HPCIM registers should be properaly configured to reflect allocated I/O and
MMIO space.
At this point BIOS has access to all the error reporting information in the system.
BIOS programs the APIC configuration registers in the MCH to allocate message space in
the processor/chipset reserved space. Identical configuration must be propagated to all
capable expander devices found during enumeration.
BIOS programs the desired SMM size, location, and configuration. At the end of this step,
set the MCH control register bit to lock-down the memory map. This prevents viruses
from reprogramming the memory configuration to compromise SMM space.
Pass to OS (cold reset) or
context recovery (S3/S4-
>S0)
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
175