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Intel^® EP80579 Integrated Processor
22.2.1.3 Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0}
Register
Table 22-6. Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register
(Sheet 1 of 2)
Description:
This register allows
when output.
reading
of
the
current
GPIO
bit
values
for
GPIO
pins
31-0
when
input,
and
writing
the
value
View: PCI
BAR: GBA(IO)
Bus:Device:Function: 0:31:0
Offset Start: 0Ch
Offset End: 0Fh
Size: 32 bit
Default: FF3F0000h
Power Well: Core^a
Bit Range
31 : 29
28 : 27
26
25 : 24
23
Bit Acronym
Bit Description
Sticky
These bits correspond to input-only GPIO in the core
well. The corresponding GP_LVL bit reflects the state of
the input signal. Writes to these bits have no effect.
GP_LVL_31_29 0 = Low
1 = High
These bits correspond to GPIO that are in the core well
and are reset to their native function by RSMRST#.
If GPIO[n] is programmed to be an output (via the
corresponding bit in the GP_IO_SEL register), then the
corresponding GP_LVL[n] bit can be updated by
software to drive a high or low value on the output pin.
If GPIO[n] is programmed as an input, then the
corresponding GP_LVL bit reflects the state of the input
GP_LVL_27_28 _{signal. Writes have no effect.}
0 = Low
1 = High
These bits correspond to GPIO that are in the Resume
well and are reset to their native function by RSMRST#
and by a writing to the CF9h register.
GP_LVL_26
This bit corresponds to input-only GPI in the core well.
The corresponding GP_LVL bit reflects the state of the
input signal. Writes to this bit have no effect.
0 = Low
1 = High
This bit corresponds to a GPI that is in the core well and
is reset to its native function by RSMRST#.
If GPIO[n] is programmed to be an output (via the
corresponding bit in the GP_IO_SEL register), then the
corresponding GP_LVL[n] bit can be updated by
software to drive a high or low value on the output pin.
If GPIO[n] is programmed as an input, then the
corresponding GP_LVL bit reflects the state of the input
GP_LVL_25_24 _{signal. Writes have no effect.}
0 = Low
1 = High
These bits correspond to GPIO that are in the Resume
well and are reset to their native function by RSMRST#
and by a writing to the CF9h register.
GP_LVL_23
The bit can be updated by software to drive a high or
low value on the output pin when used as GPIO
function.
0 = Low
1 = High
The corresponding GPIO pin is an input when used as
IRQ. This bit correspond to GPIO that is in the core well
and is reset to its native function by PLTRST#.
Bit Reset
Value
111b
11b
1b
11b
0h
Bit Access
RO
RW
RO
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
809