EP80579 Datasheet, PDF (383/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 15-12 defines the legal relationships between link and attached device power
states.
Table 15-12. Relationship Between Link and Device PM States
Downstream Component
D-State
Permissible Upstream
Component D-State
Permissible Interconnect
L-State
D0
D0
L0, L0s, L1^†
D1
D0, D1
L1
D2
D0, D1, D2
L1
D3_hot
D0, D1, D2, D3 _hot
L1, L2/L3 Ready
D3_cold
D0, D1, D2, D3 _hot, D3 _cold
L2, L3
†
Entry into L0s or L1 while attached devices remain in D0 only occurs as a part of ASPM. Per the PCI
Express spec, L0s support is mandatory, while L1 is optional. L1 is not supported by ASPM.
Several new semantics are introduced with PCI Express to support PCI-PMI compatible
software managed device and link power state transitions. The majority of the new
functionality is to accommodate an essentially edge-triggered, in-band message
scheme supporting multi chassis cabled system topologies, which must replace the
function of traditional level-sensitive board traces for PM event and wake signaling.
Further details about PME signaling appears in Section 15.3.5, “PME Support” on
page 385.
The IMCH supports messaging to facilitate transition of attached PCI Express devices to
power states D0, D1, D2, and D3 (both D3_HOT and D3_COLD). All attached devices are
required by the PCI Express Specification to support the D0 and both D3 states, while
D1 and D2 support are optional. Software should confirm device support of the optional
D1 and D2 states prior to attempting their use on any attached PCI Express device.
In the D1, D2, and D3_HOT states, the attached device is required to suppress initiation
of any link traffic other than PME initiation (if enabled) as a master, and must only
accept configuration transactions as a target. Functional context is maintained in the
D1 and D2 states, such that full initialization of the attached device is not required
upon the wake-up transition back to the D0 state. In both D3 states, functional context
is not maintained, and full initialization is required after a transition back to D0.
Placing an attached device into a low power state results in automatic transition of the
associated PCI Express port to its L1, L2 or L3 link state (depending upon the device
power state). To save additional power in the L2 state, the platform power manager
must remove the reference clock from the link. The IMCH does not provide the
necessary internal clock generation and distribution control to allow clock removal from
one PCI Express port interface without impacting the operation of its peer ports on the
IMCH. CMI does not provide support on its PCI Express link interfaces for the in-band
“tone” required to wake from such a state.
15.3.3.3
Hardware Controlled PCI Express Link States
Active-state power management (ASPM) support is a required component of PCI
Express Specification compliance and is intended to provide granularity and flexibility
for PCI Express components to dynamically manage their own power consumption
without software supervision and support. All native PCI Express components,
regardless of device class, must support active transitions to and from the L0s low
power link state as a minimum and may optionally support active transitions to and
from the L1 low power link state.
The IMCH does not support ASPM entry into the L1 state under hardware control. CMI
negatively acknowledges (NAK) ASPM requests for L1 state transitions. IMCH
configuration registers reflect this level of support for ASPM.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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