EP80579 Datasheet, PDF (183/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.0
7.1
7.1.1
Register Summary
Overview of Register Descriptions and Summaries
This chapter presents summary tables for the registers and MMIO spaces that the
components of the EP80579 define. In addition, this chapter describes how to read the
standard register description that is used throughout this document to describe the
functionality of individual registers.
The register summaries in this document follow a general formatting structure that
includes, for each register, its name, default value, offsets, and a cross-reference to its
detailed register description. Locations that are not associated with a register in the
summary table should be assumed to be reserved.
The summaries in this chapter are organized by functional unit and describe the
EP80579 registers that are visible from the IA platform perspective (e.g., PCI registers,
PCI memory-mapped I/O registers, fixed IA I/O space registers, etc.).
Register Description Tables
In addition to the summaries in this chapter, this document uses a standard tabular
format to describe the operation of each register in the device. These descriptions are
cross-referenced from summary tables and cover the specific content and functionality
of a register. The information in a register description table can be broken down into
three major areas:
• Materialization information that establishes how the register appears to software.
• Global information that lists the size, default, value, power well, etc. for the
register.
• Field definitions that list the name, description, default value, and attributes of all
the fields in the register.
The register definition can describe a unique register entity in the design or serve as a
template that describes several register entities are instantiated in the design. The
materialization information in the register description table can handle common
scenarios with minimal duplication of content:
• A single physical register that materializes at multiple “addresses” in the system
(i.e., a double- or triple-mapped register).
• Multiple physical registers that share the same definition but materialize within
different “device” instances.
• Multiple physical registers that share the same definition but materialize repeatedly
within a single “device”.
The register description table format handles the first two scenarios through “views”
that make up the bulk of the materialization information in a register description table
and handles the final scenario through a set of “repeated register” conventions.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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