EP80579 Datasheet, PDF (1630/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.5.2.1
41.5.2.2
41.5.2.3
type can be received until the snapshot indication is cleared by firmware. Thus, the
setting of the indication is a lockout of further snapshots of a particular type until
firmware takes action (unless the traffic analyzer lock inhibit feature is enabled).
Sync Messages
The SW for the master channel sends a Sync message periodically over the network at
1-, 2-, 8-, 16-, or 64-second intervals.
If the channel is a master, the Time Sync logic will monitor the interface and detect
when a Sync message has been transmitted. When a Sync message is detected and the
XMIT_Snapshot is not locked out, the message is time stamped and the current system
time is captured in the XMIT_Snapshot register. If the message is transmitted with no
errors, the XMIT_Snapshot is locked.
If the channel is a slave, the Time Sync logic will monitor the interface and detect when
a Sync message has been received. When the Sync message is detected and the
RECV_Snapshot is not locked out, the message is time stamped and the current system
time is captured in the RECV_Snapshot register. If the message is received with no
errors, the RECV_Snapshot is locked.
When the snapshot of the Sync message has occurred, an indication asserts in the
TS_Channel_Event register and remains set until firmware explicitly writes a ‘1’ back to
that bit. Until the Sync message snapshot indication is cleared, no further Sync
messages will be time stamped. Locking can be inhibited by setting the
TS_Channel_Control register appropriately.
Follow-up Messages
The Time Sync logic performs no action related to Follow-up messages. It is the
responsibility of the SW for the Master to read the XMIT_Snapshot register and send
the Follow-up message containing this timestamp.
Delay_Req Message
Slave channels transmit a Delay_Req message to the master in response to receiving a
Sync message.
If the channel is a master, the Time Sync logic will monitor the interface and detect
when a Delay_Req message has been received. When the message is detected and the
RECV_Snapshot is not locked out, the message is time stamped and the current system
time is captured in the RECV_Snapshot register. If the message is received with no
errors, the RECV_Snapshot is locked.
If the channel is a slave, the Time Sync logic will monitor the interface and detect when
a Delay_Req message has been transmitted. When the message is detected and the
XMIT_Snapshot is not locked out, the message is time stamped and the current system
time is captured in the XMIT_Snapshot register. If the message is transmitted with no
errors, the XMIT_Snapshot is locked.
When the snapshot for the Delay_Req message has occurred, an indication asserts in
the TS_Channel_Event register and remains set until firmware explicitly writes a ‘1’
back to that bit. Until the Delay_Req message snapshot indication is cleared, no further
Delay_Req messages will be time stamped. This is important to note since multiple
slave channels may try to send Delay_Req messages simultaneously. Locking can be
inhibited by setting the TS_Channel_Control register appropriately.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1630
August 2009
Order Number: 320066-003US