EP80579 Datasheet, PDF (699/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 17-16. Offset 01A4h: LCAP - Link Capabilities Register (Sheet 2 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 01A4h
Offset End: 01A7h
Size: 32 bit
Default: 0012441h
Power Well: Core
Bit Range
11 :10
09 :04
03 :00
Bit Acronym
Bit Description
APMS
MLW
MLS
The EP80579 does not support L0s or L1.
Active State Link PM Support: Indicates the level of
active state power management on NSI.
Bits
Definition
00
Neither L0s nor L1 supported
01
L0s Entry supported
(Per PCI Express spec, L0s must be supported, but the
EP80579 has defeatured L0s.)
10
Reserved: L1 Entry not supported on NSI
11
Reserved: L1 Entry not supported on NSI
Maximum Link Width: Indicates the maximum link
width is four ports.
Maximum Link Speed: Indicates the link speed is 2.5
Gbits/s.
Sticky
Bit Reset
Value
1h
4h
1h
Bit Access
RWO
RO
RO
17.1.3.3 Offset 01A8h: LCTL - Link Control Register
Table 17-17. Offset 01A8h: LCTL - Link Control Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 01A8h
Offset End: 01A9h
Size: 16 bit
Default: 0h
Power Well: Core
Bit Range
15 :08
07 :07
06 :02
01 :00
Bit Acronym
Bit Description
Sticky
Reserved
Reserved
APMC
Reserved
Reserved
Reserved
L0s has been defeatured on WL, and ASPM must never be
turned on.
Active State Link PM Control: Indicates whether NSI
must enter L0s or L1 or both.
Bits Definition
00 Disabled
01 L0s Entry Enabled
10 L1 Entry Enabled
11 L0s and L1 Entry Enabled
Bit Reset
Value
00h
0
0h
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
699