EP80579 Datasheet, PDF (1228/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.28 Offset 3Ch: IRQL – Interrupt Line Register
Table 34-30. Offset 3Ch: IRQL: Interrupt Line Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 0
Power Well: Core
Bit Range Bit Acronym
07 : 00
IRQL
Interrupt Line
Bit Description
Sticky
Bit Reset
Value
0h
Bit Access
RO
34.2.2.29 Offset 3Dh: IRQP – Interrupt Pin Register
Table 34-31. Offset 3Dh: IRQP: Interrupt Pin Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 3Dh
Offset End: 3Dh
Size: 8 bit
Default: 0
Power Well: Core
Bit Range Bit Acronym
07 : 00
IRQP
Interrupt Pin
Bit Description
Sticky
Bit Reset
Value
1
Bit Access
RO
34.2.2.30 Offset 3Eh: BCTL – Bridge Control Register
Bits in this register such as VGA Enable and ISA Enable are RW bits for software
compatibility, but don’t affect the behavior of the bridge.
Table 34-32. Offset 3Eh: BCTL: Bridge Control Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 3Eh
Offset End: 3Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 12
11
10
09
08
07
06
IRQP
DTSE
DTS
SDT
PDT
FB2B
SECR
Interrupt Pin
Discard Timer SERR Enable
Discard Timer Status
Secondary Discard Timer
Primary Discard Timer
Fast Back to Back Enable
Secondary Bus Reset
Sticky
Bit Reset
Value
0
0h
0h
0h
0h
0h
0h
Bit Access
RO
RO
RO
RO
RO
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1228
August 2009
Order Number: 320066-003US